Lines Matching defs:dsc_cfg
58 * @dsc_cfg:
70 const struct drm_dsc_config *dsc_cfg)
82 dsc_cfg->dsc_version_minor |
83 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
89 dsc_cfg->line_buf_depth |
90 dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
94 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
96 dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
97 dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
98 dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
99 dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
103 (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
113 pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
116 pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
119 pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
122 pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
125 pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
129 ((dsc_cfg->initial_xmit_delay &
135 (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
139 cpu_to_be16(dsc_cfg->initial_dec_delay);
145 dsc_cfg->initial_scale_value;
149 cpu_to_be16(dsc_cfg->scale_increment_interval);
153 ((dsc_cfg->scale_decrement_interval &
159 (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
165 dsc_cfg->first_line_bpg_offset;
169 cpu_to_be16(dsc_cfg->nfl_bpg_offset);
173 cpu_to_be16(dsc_cfg->slice_bpg_offset);
177 cpu_to_be16(dsc_cfg->initial_offset);
180 pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
183 pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
186 pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
197 dsc_cfg->rc_quant_incr_limit0;
201 dsc_cfg->rc_quant_incr_limit1;
210 dsc_cfg->rc_buf_thresh[i];
219 cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp <<
221 (dsc_cfg->rc_range_params[i].range_max_qp <<
223 (dsc_cfg->rc_range_params[i].range_bpg_offset));
227 pps_payload->native_422_420 = dsc_cfg->native_422 |
228 dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
232 dsc_cfg->second_line_bpg_offset;
236 cpu_to_be16(dsc_cfg->nsl_bpg_offset);
240 cpu_to_be16(dsc_cfg->second_line_offset_adj);