Lines Matching refs:tc
285 static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
292 return regmap_read_poll_timeout(tc->regmap, addr, val,
297 static int tc_aux_wait_busy(struct tc_data *tc)
299 return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000);
302 static int tc_aux_write_data(struct tc_data *tc, const void *data,
310 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
317 static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
322 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
346 struct tc_data *tc = aux_to_tc(aux);
352 ret = tc_aux_wait_busy(tc);
363 ret = tc_aux_write_data(tc, msg->buffer, size);
373 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
377 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
381 ret = tc_aux_wait_busy(tc);
385 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
405 return tc_aux_read_data(tc, msg->buffer, size);
430 static u32 tc_srcctrl(struct tc_data *tc)
438 if (tc->link.scrambler_dis)
440 if (tc->link.spread)
442 if (tc->link.num_lanes == 2)
444 if (tc->link.rate != 162000)
449 static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
453 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
463 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
476 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
524 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
529 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
531 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
544 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
555 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
560 return tc_pllupdate(tc, PXL_PLLCTRL);
563 static int tc_pxl_pll_dis(struct tc_data *tc)
566 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
569 static int tc_stream_clock_calc(struct tc_data *tc)
586 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
589 static int tc_set_syspllparam(struct tc_data *tc)
594 rate = clk_get_rate(tc->refclk);
609 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
613 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
616 static int tc_aux_link_setup(struct tc_data *tc)
622 ret = tc_set_syspllparam(tc);
626 ret = regmap_write(tc->regmap, DP_PHY_CTRL,
634 ret = tc_pllupdate(tc, DP0_PLLCTRL);
638 ret = tc_pllupdate(tc, DP1_PLLCTRL);
642 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000);
644 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
655 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
661 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
665 static int tc_get_display_props(struct tc_data *tc)
673 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
678 revision = tc->link.dpcd[DP_DPCD_REV];
679 rate = drm_dp_max_link_rate(tc->link.dpcd);
680 num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
683 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
687 tc->link.rate = rate;
690 dev_dbg(tc->dev, "Falling to 2 lanes\n");
694 tc->link.num_lanes = num_lanes;
696 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®);
699 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
701 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®);
705 tc->link.scrambler_dis = false;
707 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®);
710 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
712 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
714 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
715 tc->link.num_lanes,
716 drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
718 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
719 tc->link.spread ? "0.5%" : "0.0%",
720 tc->link.scrambler_dis ? "disabled" : "enabled");
721 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
722 tc->link.assr, tc->assr);
727 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
731 static int tc_set_video_mode(struct tc_data *tc,
756 out_bw = tc->link.num_lanes * tc->link.rate;
759 dev_dbg(tc->dev, "set mode %dx%d\n",
761 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
763 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
765 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
774 ret = regmap_write(tc->regmap, VPCTRL0,
780 ret = regmap_write(tc->regmap, HTIM01,
786 ret = regmap_write(tc->regmap, HTIM02,
792 ret = regmap_write(tc->regmap, VTIM01,
798 ret = regmap_write(tc->regmap, VTIM02,
804 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
809 ret = regmap_write(tc->regmap, TSTCTL,
820 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
824 ret = regmap_write(tc->regmap, DP0_TOTALVAL,
830 ret = regmap_write(tc->regmap, DP0_STARTVAL,
836 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
851 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
855 ret = regmap_write(tc->regmap, DPIPXLFMT,
862 ret = regmap_write(tc->regmap, DP0_MISC,
872 static int tc_wait_link_training(struct tc_data *tc)
877 ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
880 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
884 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
891 static int tc_main_link_enable(struct tc_data *tc)
893 struct drm_dp_aux *aux = &tc->aux;
894 struct device *dev = tc->dev;
900 dev_dbg(tc->dev, "link enable\n");
902 ret = regmap_read(tc->regmap, DP0CTL, &value);
907 ret = regmap_write(tc->regmap, DP0CTL, 0);
912 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
916 ret = regmap_write(tc->regmap, DP1_SRCCTRL,
917 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
918 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
922 ret = tc_set_syspllparam(tc);
928 if (tc->link.num_lanes == 2)
931 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
936 ret = tc_pllupdate(tc, DP0_PLLCTRL);
940 ret = tc_pllupdate(tc, DP1_PLLCTRL);
946 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
949 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
951 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000);
958 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
967 * check is tc configured for same mode
969 if (tc->assr != tc->link.assr) {
971 tc->assr);
973 tmp[0] = tc->assr;
982 if (tmp[0] != tc->assr) {
984 tc->assr);
986 tc->link.scrambler_dis = true;
991 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
992 tmp[1] = tc->link.num_lanes;
994 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1002 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
1019 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1025 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
1032 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1033 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1040 ret = regmap_write(tc->regmap, DP0CTL,
1041 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
1048 ret = tc_wait_link_training(tc);
1053 dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1061 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1067 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1068 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1075 ret = tc_wait_link_training(tc);
1080 dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1095 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
1102 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1117 dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1121 if (tc->link.num_lanes == 2) {
1125 dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1130 dev_err(tc->dev, "Interlane align failed\n");
1147 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1150 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1154 static int tc_main_link_disable(struct tc_data *tc)
1158 dev_dbg(tc->dev, "link disable\n");
1160 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
1164 return regmap_write(tc->regmap, DP0CTL, 0);
1167 static int tc_stream_enable(struct tc_data *tc)
1172 dev_dbg(tc->dev, "enable video stream\n");
1176 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1177 1000 * tc->mode.clock);
1182 ret = tc_set_video_mode(tc, &tc->mode);
1187 ret = tc_stream_clock_calc(tc);
1192 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1194 ret = regmap_write(tc->regmap, DP0CTL, value);
1206 ret = regmap_write(tc->regmap, DP0CTL, value);
1215 ret = regmap_write(tc->regmap, SYSCTRL, value);
1222 static int tc_stream_disable(struct tc_data *tc)
1226 dev_dbg(tc->dev, "disable video stream\n");
1228 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
1232 tc_pxl_pll_dis(tc);
1239 struct tc_data *tc = bridge_to_tc(bridge);
1242 ret = tc_get_display_props(tc);
1244 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1248 ret = tc_main_link_enable(tc);
1250 dev_err(tc->dev, "main link enable error: %d\n", ret);
1254 ret = tc_stream_enable(tc);
1256 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1257 tc_main_link_disable(tc);
1264 struct tc_data *tc = bridge_to_tc(bridge);
1267 ret = tc_stream_disable(tc);
1269 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1271 ret = tc_main_link_disable(tc);
1273 dev_err(tc->dev, "main link disable error: %d\n", ret);
1292 struct tc_data *tc = bridge_to_tc(bridge);
1301 avail = tc->link.num_lanes * tc->link.rate;
1313 struct tc_data *tc = bridge_to_tc(bridge);
1315 tc->mode = *mode;
1321 struct tc_data *tc = bridge_to_tc(bridge);
1323 return drm_get_edid(connector, &tc->aux.ddc);
1328 struct tc_data *tc = connector_to_tc(connector);
1333 ret = tc_get_display_props(tc);
1335 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1339 if (tc->panel_bridge) {
1340 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector);
1345 edid = tc_get_edid(&tc->bridge, connector);
1358 struct tc_data *tc = bridge_to_tc(bridge);
1363 ret = regmap_read(tc->regmap, GPIOI, &val);
1367 conn = val & BIT(tc->hpd_pin);
1378 struct tc_data *tc = connector_to_tc(connector);
1380 if (tc->hpd_pin >= 0)
1381 return tc_bridge_detect(&tc->bridge);
1383 if (tc->panel_bridge)
1402 struct tc_data *tc = bridge_to_tc(bridge);
1406 if (tc->panel_bridge) {
1408 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1409 &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1418 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1419 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type);
1424 if (tc->hpd_pin >= 0) {
1425 if (tc->have_irq)
1426 tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1428 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1432 drm_display_info_set_bus_formats(&tc->connector.display_info,
1434 tc->connector.display_info.bus_flags =
1438 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1497 struct tc_data *tc = arg;
1501 r = regmap_read(tc->regmap, INTSTS_G, &val);
1511 regmap_read(tc->regmap, SYSSTAT, &stat);
1513 dev_err(tc->dev, "syserr %x\n", stat);
1516 if (tc->hpd_pin >= 0 && tc->bridge.dev) {
1523 bool h = val & INT_GPIO_H(tc->hpd_pin);
1524 bool lc = val & INT_GPIO_LC(tc->hpd_pin);
1526 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
1530 drm_kms_helper_hotplug_event(tc->bridge.dev);
1533 regmap_write(tc->regmap, INTSTS_G, val);
1538 static int tc_probe_edp_bridge_endpoint(struct tc_data *tc)
1540 struct device *dev = tc->dev;
1556 tc->panel_bridge = panel_bridge;
1557 tc->bridge.type = DRM_MODE_CONNECTOR_eDP;
1559 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
1575 struct tc_data *tc;
1578 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1579 if (!tc)
1582 tc->dev = dev;
1584 ret = tc_probe_edp_bridge_endpoint(tc);
1588 tc->refclk = devm_clk_get(dev, "ref");
1589 if (IS_ERR(tc->refclk)) {
1590 ret = PTR_ERR(tc->refclk);
1595 ret = clk_prepare_enable(tc->refclk);
1599 ret = devm_add_action_or_reset(dev, tc_clk_disable, tc->refclk);
1607 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1608 if (IS_ERR(tc->sd_gpio))
1609 return PTR_ERR(tc->sd_gpio);
1611 if (tc->sd_gpio) {
1612 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1617 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1618 if (IS_ERR(tc->reset_gpio))
1619 return PTR_ERR(tc->reset_gpio);
1621 if (tc->reset_gpio) {
1622 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1626 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1627 if (IS_ERR(tc->regmap)) {
1628 ret = PTR_ERR(tc->regmap);
1634 &tc->hpd_pin);
1636 tc->hpd_pin = -ENODEV;
1638 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
1646 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
1651 "tc358767-irq", tc);
1657 tc->have_irq = true;
1660 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1662 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1666 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1667 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1671 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1673 if (!tc->reset_gpio) {
1680 regmap_update_bits(tc->regmap, SYSRSTENB,
1683 regmap_update_bits(tc->regmap, SYSRSTENB,
1689 if (tc->hpd_pin >= 0) {
1690 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
1691 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
1694 regmap_write(tc->regmap, lcnt_reg,
1695 clk_get_rate(tc->refclk) * 2 / 1000);
1697 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
1699 if (tc->have_irq) {
1701 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
1705 ret = tc_aux_link_setup(tc);
1710 tc->aux.name = "TC358767 AUX i2c adapter";
1711 tc->aux.dev = tc->dev;
1712 tc->aux.transfer = tc_aux_transfer;
1713 ret = drm_dp_aux_register(&tc->aux);
1717 tc->bridge.funcs = &tc_bridge_funcs;
1718 if (tc->hpd_pin >= 0)
1719 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT;
1720 tc->bridge.ops |= DRM_BRIDGE_OP_EDID;
1722 tc->bridge.of_node = dev->of_node;
1723 drm_bridge_add(&tc->bridge);
1725 i2c_set_clientdata(client, tc);
1732 struct tc_data *tc = i2c_get_clientdata(client);
1734 drm_bridge_remove(&tc->bridge);
1735 drm_dp_aux_unregister(&tc->aux);