Lines Matching defs:refclk
261 struct clk *refclk;
457 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
463 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
477 refclk);
482 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
483 * We don't allow any refclk > 200 MHz, only check lower bounds.
485 if (refclk / ext_div[i_pre] < 1000000)
494 do_div(tmp, refclk);
501 clk = (refclk / ext_div[i_pre] / div) * mul;
503 * refclk * mul / (ext_pre_div * pre_div)
531 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
535 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
594 rate = clk_get_rate(tc->refclk);
609 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
1176 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1567 struct clk *refclk = data;
1569 clk_disable_unprepare(refclk);
1588 tc->refclk = devm_clk_get(dev, "ref");
1589 if (IS_ERR(tc->refclk)) {
1590 ret = PTR_ERR(tc->refclk);
1591 dev_err(dev, "Failed to get refclk: %d\n", ret);
1595 ret = clk_prepare_enable(tc->refclk);
1599 ret = devm_add_action_or_reset(dev, tc_clk_disable, tc->refclk);
1695 clk_get_rate(tc->refclk) * 2 / 1000);