Lines Matching refs:dsi
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
226 #define VPG_DEFS(name, dsi) \
227 ((void __force *)&((*dsi).vpg_defs.name))
229 #define REGISTER(name, mask, dsi) \
230 { #name, VPG_DEFS(name, dsi), mask, dsi }
236 struct dw_mipi_dsi *dsi;
265 struct dw_mipi_dsi *master; /* dual-dsi master ptr */
266 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
274 static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi)
276 return dsi->slave || dsi->master;
302 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
304 writel(val, dsi->base + reg);
307 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
309 return readl(dsi->base + reg);
315 struct dw_mipi_dsi *dsi = host_to_dsi(host);
316 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
321 if (device->lanes > dsi->plat_data->max_data_lanes) {
322 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
327 dsi->lanes = device->lanes;
328 dsi->channel = device->channel;
329 dsi->format = device->format;
330 dsi->mode_flags = device->mode_flags;
344 dsi->panel_bridge = bridge;
346 drm_bridge_add(&dsi->bridge);
360 struct dw_mipi_dsi *dsi = host_to_dsi(host);
361 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
372 drm_bridge_remove(&dsi->bridge);
377 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
389 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(16)
397 dsi_write(dsi, DSI_CMD_MODE_CFG, val);
399 val = dsi_read(dsi, DSI_VID_MODE_CFG);
404 dsi_write(dsi, DSI_VID_MODE_CFG, val);
407 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
412 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
416 dev_err(dsi->dev, "failed to get available command FIFO\n");
420 dsi_write(dsi, DSI_GEN_HDR, hdr_val);
423 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
427 dev_err(dsi->dev, "failed to write command FIFO\n");
434 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
446 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
450 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
455 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
459 dev_err(dsi->dev,
467 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
470 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
478 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
482 dev_err(dsi->dev, "Timeout during read operation\n");
488 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
492 dev_err(dsi->dev, "Read payload FIFO is empty\n");
496 val = dsi_read(dsi, DSI_GEN_PLD_DATA);
507 struct dw_mipi_dsi *dsi = host_to_dsi(host);
513 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
517 dw_mipi_message_config(dsi, msg);
518 if (dsi->slave)
519 dw_mipi_message_config(dsi->slave, msg);
521 ret = dw_mipi_dsi_write(dsi, &packet);
524 if (dsi->slave) {
525 ret = dw_mipi_dsi_write(dsi->slave, &packet);
531 ret = dw_mipi_dsi_read(dsi, msg);
548 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
559 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
561 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
567 if (dsi->vpg_defs.vpg) {
569 val |= dsi->vpg_defs.vpg_horizontal ?
571 val |= dsi->vpg_defs.vpg_ber_pattern ? VID_MODE_VPG_MODE : 0;
575 dsi_write(dsi, DSI_VID_MODE_CFG, val);
578 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
583 dsi_write(dsi, DSI_PWR_UP, RESET);
586 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
587 dw_mipi_dsi_video_mode_config(dsi);
589 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
593 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
595 dsi_write(dsi, DSI_LPCLK_CTRL, val);
597 dsi_write(dsi, DSI_PWR_UP, POWERUP);
600 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
602 dsi_write(dsi, DSI_PWR_UP, RESET);
603 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
606 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
608 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
618 ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data,
631 esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;
633 dsi_write(dsi, DSI_PWR_UP, RESET);
640 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
644 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
649 switch (dsi->format) {
669 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
670 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
671 dsi_write(dsi, DSI_DPI_CFG_POL, val);
674 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
676 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
679 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
690 dsi_write(dsi, DSI_VID_PKT_SIZE,
691 dw_mipi_is_dual_mode(dsi) ?
696 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
703 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
709 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
710 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
714 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
720 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
730 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
743 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
744 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
746 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
747 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
749 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
750 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
753 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
763 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
764 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
765 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
766 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
769 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
771 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
776 ret = phy_ops->get_timing(dsi->plat_data->priv_data,
777 dsi->lane_mbps, &timing);
779 DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n");
789 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
792 dsi_write(dsi, DSI_PHY_TMR_CFG,
795 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
797 dsi_write(dsi, DSI_PHY_TMR_CFG,
803 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
808 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
812 * stop wait time should be the maximum between host dsi
815 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
816 N_LANES(dsi->lanes));
819 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
822 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
824 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
825 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
826 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
829 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
834 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
837 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
842 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
849 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
851 dsi_read(dsi, DSI_INT_ST0);
852 dsi_read(dsi, DSI_INT_ST1);
853 dsi_write(dsi, DSI_INT_MSK0, 0);
854 dsi_write(dsi, DSI_INT_MSK1, 0);
859 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
860 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
868 dw_mipi_dsi_set_mode(dsi, 0);
872 * panel unprepare before the dsi "final" disable...
876 if (dsi->panel_bridge->funcs->post_disable)
877 dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
880 phy_ops->power_off(dsi->plat_data->priv_data);
882 if (dsi->slave) {
883 dw_mipi_dsi_disable(dsi->slave);
884 clk_disable_unprepare(dsi->slave->pclk);
885 pm_runtime_put(dsi->slave->dev);
887 dw_mipi_dsi_disable(dsi);
889 clk_disable_unprepare(dsi->pclk);
890 pm_runtime_put(dsi->dev);
893 static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi)
896 if (dsi->master)
897 return dsi->master->lanes + dsi->lanes;
900 if (dsi->slave)
901 return dsi->lanes + dsi->slave->lanes;
903 /* single-dsi, so no other instance to consider */
904 return dsi->lanes;
907 static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi,
910 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
911 void *priv_data = dsi->plat_data->priv_data;
913 u32 lanes = dw_mipi_dsi_get_lanes(dsi);
915 clk_prepare_enable(dsi->pclk);
917 ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags,
918 lanes, dsi->format, &dsi->lane_mbps);
922 pm_runtime_get_sync(dsi->dev);
923 dw_mipi_dsi_init(dsi);
924 dw_mipi_dsi_dpi_config(dsi, adjusted_mode);
925 dw_mipi_dsi_packet_handler_config(dsi);
926 dw_mipi_dsi_video_mode_config(dsi);
927 dw_mipi_dsi_video_packet_config(dsi, adjusted_mode);
928 dw_mipi_dsi_command_mode_config(dsi);
929 dw_mipi_dsi_line_timer_config(dsi, adjusted_mode);
930 dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode);
932 dw_mipi_dsi_dphy_init(dsi);
933 dw_mipi_dsi_dphy_timing_config(dsi);
934 dw_mipi_dsi_dphy_interface_config(dsi);
936 dw_mipi_dsi_clear_err(dsi);
942 dw_mipi_dsi_dphy_enable(dsi);
947 dw_mipi_dsi_set_mode(dsi, 0);
950 phy_ops->power_on(dsi->plat_data->priv_data);
957 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
959 dw_mipi_dsi_mode_set(dsi, adjusted_mode);
960 if (dsi->slave)
961 dw_mipi_dsi_mode_set(dsi->slave, adjusted_mode);
966 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
969 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
970 if (dsi->slave)
971 dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO);
979 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
980 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
992 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
1002 /* Attach the panel-bridge to the dsi bridge */
1003 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge,
1020 struct dw_mipi_dsi *dsi;
1026 dsi = vpg->dsi;
1030 mode_cfg = dsi_read(dsi, DSI_VID_MODE_CFG);
1037 dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg);
1059 struct dw_mipi_dsi *dsi = data;
1061 REGISTER(vpg, VID_MODE_VPG_ENABLE, dsi),
1062 REGISTER(vpg_horizontal, VID_MODE_VPG_HORIZONTAL, dsi),
1063 REGISTER(vpg_ber_pattern, VID_MODE_VPG_MODE, dsi),
1067 dsi->debugfs_vpg = kmemdup(debugfs, sizeof(debugfs), GFP_KERNEL);
1068 if (!dsi->debugfs_vpg)
1072 debugfs_create_file(dsi->debugfs_vpg[i].name, 0644,
1073 dsi->debugfs, &dsi->debugfs_vpg[i],
1077 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi)
1079 dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL);
1080 if (IS_ERR(dsi->debugfs)) {
1081 dev_err(dsi->dev, "failed to create debugfs root\n");
1085 debugfs_create_files(dsi);
1088 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi)
1090 debugfs_remove_recursive(dsi->debugfs);
1091 kfree(dsi->debugfs_vpg);
1096 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { }
1097 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
1107 struct dw_mipi_dsi *dsi;
1110 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1111 if (!dsi)
1114 dsi->dev = dev;
1115 dsi->plat_data = plat_data;
1124 dsi->base = devm_platform_ioremap_resource(pdev, 0);
1125 if (IS_ERR(dsi->base))
1129 dsi->base = plat_data->base;
1132 dsi->pclk = devm_clk_get(dev, "pclk");
1133 if (IS_ERR(dsi->pclk)) {
1134 ret = PTR_ERR(dsi->pclk);
1154 ret = clk_prepare_enable(dsi->pclk);
1164 clk_disable_unprepare(dsi->pclk);
1167 dw_mipi_dsi_debugfs_init(dsi);
1170 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1171 dsi->dsi_host.dev = dev;
1172 ret = mipi_dsi_host_register(&dsi->dsi_host);
1176 dw_mipi_dsi_debugfs_remove(dsi);
1180 dsi->bridge.driver_private = dsi;
1181 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
1183 dsi->bridge.of_node = pdev->dev.of_node;
1186 return dsi;
1189 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
1191 mipi_dsi_host_unregister(&dsi->dsi_host);
1193 pm_runtime_disable(dsi->dev);
1194 dw_mipi_dsi_debugfs_remove(dsi);
1197 void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave)
1200 dsi->slave = slave;
1201 dsi->slave->master = dsi;
1204 dsi->slave->lanes = dsi->lanes;
1205 dsi->slave->channel = dsi->channel;
1206 dsi->slave->format = dsi->format;
1207 dsi->slave->mode_flags = dsi->mode_flags;
1222 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
1224 __dw_mipi_dsi_remove(dsi);
1231 int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder)
1235 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0);
1245 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
1254 MODULE_ALIAS("platform:dw-mipi-dsi");