Lines Matching refs:dsi
33 #include "nwl-dsi.h"
35 #define DRV_NAME "nwl-dsi"
111 /* dsi lanes */
134 static int nwl_dsi_clear_error(struct nwl_dsi *dsi)
136 int ret = dsi->error;
138 dsi->error = 0;
142 static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val)
146 if (dsi->error)
149 ret = regmap_write(dsi->regmap, reg, val);
151 DRM_DEV_ERROR(dsi->dev,
154 dsi->error = ret;
158 static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg)
163 if (dsi->error)
166 ret = regmap_read(dsi->regmap, reg, &val);
168 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n",
170 dsi->error = ret;
194 static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps)
196 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
198 return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp,
199 dsi->lanes * 8ULL * NSEC_PER_SEC);
205 static u32 ui2bc(struct nwl_dsi *dsi, unsigned long long ui)
207 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
209 return DIV64_U64_ROUND_UP(ui * dsi->lanes,
210 dsi->mode.clock * 1000 * bpp);
221 static int nwl_dsi_config_host(struct nwl_dsi *dsi)
224 struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy;
226 if (dsi->lanes < 1 || dsi->lanes > 4)
229 DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes);
230 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);
232 if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
233 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01);
234 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01);
236 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00);
237 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00);
241 cycles = ui2bc(dsi, cfg->clk_pre);
242 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles);
243 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles);
244 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);
245 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles);
246 cycles += ui2bc(dsi, cfg->clk_pre);
247 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles);
248 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles);
249 cycles = ps2bc(dsi, cfg->hs_exit);
250 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);
251 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);
253 nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01);
254 nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00);
255 nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00);
256 nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00);
259 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles);
260 nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles);
262 return nwl_dsi_clear_error(dsi);
265 static int nwl_dsi_config_dpi(struct nwl_dsi *dsi)
273 hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay;
274 hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start;
275 hback_porch = dsi->mode.htotal - dsi->mode.hsync_end;
277 vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay;
278 vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start;
279 vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end;
281 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch);
282 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch);
283 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len);
284 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay);
285 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch);
286 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch);
287 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len);
288 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay);
289 DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock);
291 color_format = nwl_dsi_get_dpi_pixel_format(dsi->format);
293 DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n",
294 dsi->format);
297 DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format);
299 nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
300 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
305 nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
307 nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
310 burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
311 !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE);
314 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE);
315 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256);
317 mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ?
320 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode);
321 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL,
322 dsi->mode.hdisplay);
325 nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch);
326 nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch);
327 nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len);
329 nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);
330 nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1);
331 nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0);
332 nwl_dsi_write(dsi, NWL_DSI_VC, 0x0);
334 nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay);
335 nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1);
336 nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch);
337 nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch);
339 return nwl_dsi_clear_error(dsi);
342 static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi)
346 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, 0xffffffff);
347 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7);
354 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable);
356 return nwl_dsi_clear_error(dsi);
362 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
363 struct device *dev = dsi->dev;
371 dsi->lanes = device->lanes;
372 dsi->format = device->format;
373 dsi->dsi_mode_flags = device->mode_flags;
378 static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status)
380 struct device *dev = dsi->dev;
381 struct nwl_dsi_transfer *xfer = dsi->xfer;
395 val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER);
396 err = nwl_dsi_clear_error(dsi);
457 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
468 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
486 err = nwl_dsi_clear_error(dsi);
493 static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status)
495 struct nwl_dsi_transfer *xfer = dsi->xfer;
508 end_packet = nwl_dsi_read_packet(dsi, status);
515 static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi)
517 struct nwl_dsi_transfer *xfer = dsi->xfer;
533 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
549 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
561 if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) {
562 DRM_DEV_DEBUG_DRIVER(dsi->dev,
572 nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val);
575 nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1);
581 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
586 dsi->xfer = &xfer;
589 dsi->xfer = NULL;
613 ret = clk_prepare_enable(dsi->rx_esc_clk);
615 DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n",
619 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n",
620 clk_get_rate(dsi->rx_esc_clk));
623 nwl_dsi_begin_transmission(dsi);
634 clk_disable_unprepare(dsi->rx_esc_clk);
647 struct nwl_dsi *dsi = data;
649 irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS);
652 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n");
655 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n");
660 nwl_dsi_finish_transmission(dsi, irq_status);
665 static int nwl_dsi_enable(struct nwl_dsi *dsi)
667 struct device *dev = dsi->dev;
668 union phy_configure_opts *phy_cfg = &dsi->phy_cfg;
671 if (!dsi->lanes) {
672 DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes);
676 ret = phy_init(dsi->phy);
682 ret = phy_configure(dsi->phy, phy_cfg);
688 ret = clk_prepare_enable(dsi->tx_esc_clk);
690 DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n",
694 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n",
695 clk_get_rate(dsi->tx_esc_clk));
697 ret = nwl_dsi_config_host(dsi);
703 ret = nwl_dsi_config_dpi(dsi);
709 ret = phy_power_on(dsi->phy);
715 ret = nwl_dsi_init_interrupts(dsi);
722 phy_power_off(dsi->phy);
724 clk_disable_unprepare(dsi->tx_esc_clk);
726 phy_exit(dsi->phy);
731 static int nwl_dsi_disable(struct nwl_dsi *dsi)
733 struct device *dev = dsi->dev;
737 phy_power_off(dsi->phy);
738 phy_exit(dsi->phy);
740 /* Disabling the clock before the phy breaks enabling dsi again */
741 clk_disable_unprepare(dsi->tx_esc_clk);
750 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
753 nwl_dsi_disable(dsi);
755 ret = reset_control_assert(dsi->rst_dpi);
757 DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret);
760 ret = reset_control_assert(dsi->rst_byte);
762 DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret);
765 ret = reset_control_assert(dsi->rst_esc);
767 DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret);
770 ret = reset_control_assert(dsi->rst_pclk);
772 DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret);
776 clk_disable_unprepare(dsi->core_clk);
777 clk_disable_unprepare(dsi->lcdif_clk);
779 pm_runtime_put(dsi->dev);
782 static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi,
789 if (dsi->lanes < 1 || dsi->lanes > 4)
794 * dphy and nwl dsi host
797 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes,
802 rate = clk_get_rate(dsi->tx_esc_clk);
803 DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate);
814 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
815 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
817 if (mode->clock * bpp > 15000000 * dsi->lanes)
820 if (mode->clock * bpp < 80000 * dsi->lanes)
849 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
850 struct device *dev = dsi->dev;
855 ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg);
863 if (new_cfg.mipi_dphy.hs_clk_rate == dsi->phy_cfg.mipi_dphy.hs_clk_rate)
866 phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);
869 memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg));
871 memcpy(&dsi->mode, adjusted_mode, sizeof(dsi->mode));
879 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
882 pm_runtime_get_sync(dsi->dev);
884 if (clk_prepare_enable(dsi->lcdif_clk) < 0)
886 if (clk_prepare_enable(dsi->core_clk) < 0)
890 ret = reset_control_deassert(dsi->rst_pclk);
892 DRM_DEV_ERROR(dsi->dev, "Failed to deassert PCLK: %d\n", ret);
897 nwl_dsi_enable(dsi);
900 ret = reset_control_deassert(dsi->rst_esc);
902 DRM_DEV_ERROR(dsi->dev, "Failed to deassert ESC: %d\n", ret);
905 ret = reset_control_deassert(dsi->rst_byte);
907 DRM_DEV_ERROR(dsi->dev, "Failed to deassert BYTE: %d\n", ret);
916 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
920 ret = reset_control_deassert(dsi->rst_dpi);
922 DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret);
928 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
933 ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel,
943 dsi->panel_bridge = panel_bridge;
945 if (!dsi->panel_bridge)
948 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge,
953 { struct nwl_dsi *dsi = bridge_to_dsi(bridge);
955 drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0);
972 static int nwl_dsi_parse_dt(struct nwl_dsi *dsi)
974 struct platform_device *pdev = to_platform_device(dsi->dev);
979 dsi->phy = devm_phy_get(dsi->dev, "dphy");
980 if (IS_ERR(dsi->phy)) {
981 ret = PTR_ERR(dsi->phy);
983 DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret);
987 clk = devm_clk_get(dsi->dev, "lcdif");
990 DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n",
994 dsi->lcdif_clk = clk;
996 clk = devm_clk_get(dsi->dev, "core");
999 DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n",
1003 dsi->core_clk = clk;
1005 clk = devm_clk_get(dsi->dev, "phy_ref");
1008 DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n",
1012 dsi->phy_ref_clk = clk;
1014 clk = devm_clk_get(dsi->dev, "rx_esc");
1017 DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n",
1021 dsi->rx_esc_clk = clk;
1023 clk = devm_clk_get(dsi->dev, "tx_esc");
1026 DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n",
1030 dsi->tx_esc_clk = clk;
1032 dsi->mux = devm_mux_control_get(dsi->dev, NULL);
1033 if (IS_ERR(dsi->mux)) {
1034 ret = PTR_ERR(dsi->mux);
1036 DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret);
1044 dsi->regmap =
1045 devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config);
1046 if (IS_ERR(dsi->regmap)) {
1047 ret = PTR_ERR(dsi->regmap);
1048 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n",
1053 dsi->irq = platform_get_irq(pdev, 0);
1054 if (dsi->irq < 0) {
1055 DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n",
1056 dsi->irq);
1057 return dsi->irq;
1060 dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk");
1061 if (IS_ERR(dsi->rst_pclk)) {
1062 DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n",
1063 PTR_ERR(dsi->rst_pclk));
1064 return PTR_ERR(dsi->rst_pclk);
1066 dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte");
1067 if (IS_ERR(dsi->rst_byte)) {
1068 DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n",
1069 PTR_ERR(dsi->rst_byte));
1070 return PTR_ERR(dsi->rst_byte);
1072 dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc");
1073 if (IS_ERR(dsi->rst_esc)) {
1074 DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n",
1075 PTR_ERR(dsi->rst_esc));
1076 return PTR_ERR(dsi->rst_esc);
1078 dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi");
1079 if (IS_ERR(dsi->rst_dpi)) {
1080 DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n",
1081 PTR_ERR(dsi->rst_dpi));
1082 return PTR_ERR(dsi->rst_dpi);
1087 static int nwl_dsi_select_input(struct nwl_dsi *dsi)
1093 remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1098 remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1101 DRM_DEV_ERROR(dsi->dev,
1107 DRM_DEV_INFO(dsi->dev, "Using %s as input source\n",
1109 ret = mux_control_try_select(dsi->mux, use_dcss);
1111 DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret);
1117 static int nwl_dsi_deselect_input(struct nwl_dsi *dsi)
1121 ret = mux_control_deselect(dsi->mux);
1123 DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret);
1133 { .compatible = "fsl,imx8mq-nwl-dsi", },
1148 struct nwl_dsi *dsi;
1151 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1152 if (!dsi)
1155 dsi->dev = dev;
1157 ret = nwl_dsi_parse_dt(dsi);
1161 ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0,
1162 dev_name(dev), dsi);
1164 DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq,
1169 dsi->dsi_host.ops = &nwl_dsi_host_ops;
1170 dsi->dsi_host.dev = dev;
1171 ret = mipi_dsi_host_register(&dsi->dsi_host);
1179 dsi->quirks = (uintptr_t)attr->data;
1181 dsi->bridge.driver_private = dsi;
1182 dsi->bridge.funcs = &nwl_dsi_bridge_funcs;
1183 dsi->bridge.of_node = dev->of_node;
1184 dsi->bridge.timings = &nwl_dsi_timings;
1186 dev_set_drvdata(dev, dsi);
1189 ret = nwl_dsi_select_input(dsi);
1192 mipi_dsi_host_unregister(&dsi->dsi_host);
1196 drm_bridge_add(&dsi->bridge);
1202 struct nwl_dsi *dsi = platform_get_drvdata(pdev);
1204 nwl_dsi_deselect_input(dsi);
1205 mipi_dsi_host_unregister(&dsi->dsi_host);
1206 drm_bridge_remove(&dsi->bridge);