Lines Matching defs:cycles
192 * ps2bc - Picoseconds to byte clock cycles
203 * ui2bc - UI time periods to byte clock cycles
214 * us2bc - micro seconds to lp clock cycles
223 u32 cycles;
240 /* values in byte clock cycles */
241 cycles = ui2bc(dsi, cfg->clk_pre);
242 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles);
243 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles);
244 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);
245 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles);
246 cycles += ui2bc(dsi, cfg->clk_pre);
247 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles);
248 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles);
249 cycles = ps2bc(dsi, cfg->hs_exit);
250 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);
251 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);
257 /* In LP clock cycles */
258 cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup);
259 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles);
260 nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles);