Lines Matching defs:mode
30 struct drm_display_mode *mode = &adv->curr_mode;
34 hsw = mode->hsync_end - mode->hsync_start;
35 hfp = mode->hsync_start - mode->hdisplay;
36 hbp = mode->htotal - mode->hsync_end;
37 vsw = mode->vsync_end - mode->vsync_start;
38 vfp = mode->vsync_start - mode->vdisplay;
39 vbp = mode->vtotal - mode->vsync_end;
41 /* set pixel clock divider mode */
46 regmap_write(adv->regmap_cec, 0x28, mode->htotal >> 4);
47 regmap_write(adv->regmap_cec, 0x29, (mode->htotal << 4) & 0xff);
56 regmap_write(adv->regmap_cec, 0x30, mode->vtotal >> 4);
57 regmap_write(adv->regmap_cec, 0x31, (mode->vtotal << 4) & 0xff);
88 /* disable test mode */
104 const struct drm_display_mode *mode)
111 if (mode->clock > (adv->type == ADV7533 ? 80000 : 148500))
117 if (mode->clock * bpp > max_lane_freq * adv->num_dsi_lanes)