Lines Matching refs:ast
42 struct ast_private *ast = to_ast_private(dev);
44 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01);
45 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01);
50 struct ast_private *ast = to_ast_private(dev);
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
58 struct ast_private *ast = to_ast_private(dev);
61 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
73 struct ast_private *ast = to_ast_private(dev);
79 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
81 if (ast->chip == AST2300 || ast->chip == AST2400 ||
82 ast->chip == AST2500) {
92 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info);
98 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */
101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
102 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
106 if (ast->chip == AST2300 || ast->chip == AST2400 ||
107 ast->chip == AST2500)
109 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
112 u32 ast_mindwm(struct ast_private *ast, u32 r)
116 ast_write32(ast, 0xf004, r & 0xffff0000);
117 ast_write32(ast, 0xf000, 0x1);
120 data = ast_read32(ast, 0xf004) & 0xffff0000;
122 return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
125 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
128 ast_write32(ast, 0xf004, r & 0xffff0000);
129 ast_write32(ast, 0xf000, 0x1);
131 data = ast_read32(ast, 0xf004) & 0xffff0000;
133 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
164 static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)
168 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
169 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
172 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
174 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
178 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
179 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
182 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
184 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
188 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
189 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
194 static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
198 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
199 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
202 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
204 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
208 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
209 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
214 static int cbrtest_ast2150(struct ast_private *ast)
219 if (mmctestburst2_ast2150(ast, i))
224 static int cbrscan_ast2150(struct ast_private *ast, int busw)
229 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
231 if (cbrtest_ast2150(ast))
241 static void cbrdlli_ast2150(struct ast_private *ast, int busw)
251 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
252 data = cbrscan_ast2150(ast, busw);
268 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
275 struct ast_private *ast = to_ast_private(dev);
280 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
283 if (ast->chip == AST2000) {
285 ast_write32(ast, 0xf004, 0x1e6e0000);
286 ast_write32(ast, 0xf000, 0x1);
287 ast_write32(ast, 0x10100, 0xa8);
291 } while (ast_read32(ast, 0x10100) != 0xa8);
293 if (ast->chip == AST2100 || ast->chip == AST2200)
298 ast_write32(ast, 0xf004, 0x1e6e0000);
299 ast_write32(ast, 0xf000, 0x1);
300 ast_write32(ast, 0x12000, 0x1688A8A8);
303 } while (ast_read32(ast, 0x12000) != 0x01);
305 ast_write32(ast, 0x10000, 0xfc600309);
308 } while (ast_read32(ast, 0x10000) != 0x01);
315 } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) {
317 if (ast->dram_type == AST_DRAM_1Gx16)
319 else if (ast->dram_type == AST_DRAM_1Gx32)
322 temp = ast_read32(ast, 0x12070);
325 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
327 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
332 data = ast_read32(ast, 0x10120);
334 data = ast_read32(ast, 0x10004);
336 cbrdlli_ast2150(ast, 16); /* 16 bits */
338 cbrdlli_ast2150(ast, 32); /* 32 bits */
341 switch (ast->chip) {
343 temp = ast_read32(ast, 0x10140);
344 ast_write32(ast, 0x10140, temp | 0x40);
350 temp = ast_read32(ast, 0x1200c);
351 ast_write32(ast, 0x1200c, temp & 0xfffffffd);
352 temp = ast_read32(ast, 0x12040);
353 ast_write32(ast, 0x12040, temp | 0x40);
362 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
368 struct ast_private *ast = to_ast_private(dev);
376 ast_open_key(ast);
380 if (ast->config_mode == ast_use_p2a) {
381 if (ast->chip == AST2500)
383 else if (ast->chip == AST2300 || ast->chip == AST2400)
390 if (ast->tx_chip_type != AST_TX_NONE)
391 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */
448 static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)
452 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
453 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
456 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
460 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
464 ast_moutdwm(ast, 0x1e6e0070, 0x0);
468 static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
472 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
473 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
476 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
478 ast_moutdwm(ast, 0x1e6e0070, 0x0);
482 data = ast_mindwm(ast, 0x1e6e0078);
484 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
489 static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
491 return mmc_test(ast, datagen, 0xc1);
494 static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)
496 return mmc_test2(ast, datagen, 0x41);
499 static bool mmc_test_single(struct ast_private *ast, u32 datagen)
501 return mmc_test(ast, datagen, 0xc5);
504 static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
506 return mmc_test2(ast, datagen, 0x05);
509 static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)
511 return mmc_test(ast, datagen, 0x85);
514 static int cbr_test(struct ast_private *ast)
518 data = mmc_test_single2(ast, 0);
522 data = mmc_test_burst2(ast, i);
533 static int cbr_scan(struct ast_private *ast)
539 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
541 if ((data = cbr_test(ast)) != 0) {
554 static u32 cbr_test2(struct ast_private *ast)
558 data = mmc_test_burst2(ast, 0);
561 data |= mmc_test_single2(ast, 0);
568 static u32 cbr_scan2(struct ast_private *ast)
574 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
576 if ((data = cbr_test2(ast)) != 0) {
589 static bool cbr_test3(struct ast_private *ast)
591 if (!mmc_test_burst(ast, 0))
593 if (!mmc_test_single(ast, 0))
598 static bool cbr_scan3(struct ast_private *ast)
603 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
605 if (cbr_test3(ast))
614 static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
625 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
626 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
627 data = cbr_scan2(ast);
684 ast_moutdwm(ast, 0x1E6E0080, data);
709 ast_moutdwm(ast, 0x1E6E0084, data);
713 static void finetuneDQSI(struct ast_private *ast)
722 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
723 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
725 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
740 ast_moutdwm(ast, 0x1E6E000C, 0);
741 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
742 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
744 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
745 ast_moutdwm(ast, 0x1E6E0070, 0);
746 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
747 if (cbr_scan3(ast)) {
800 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
803 static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
808 finetuneDQSI(ast);
809 if (finetuneDQI_L(ast, param) == false)
817 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
818 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
819 data = cbr_scan(ast);
855 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
859 static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
863 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
866 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
880 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
908 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
938 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
968 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
982 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
996 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
1012 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1030 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1048 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1101 static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1106 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1107 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1108 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1109 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1111 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1112 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1114 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1117 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1118 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1119 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1120 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1121 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1122 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1123 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1124 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1125 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1126 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1127 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1128 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1129 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1130 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1131 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1132 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1133 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1134 ast_moutdwm(ast, 0x1E6E0054, 0);
1135 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1136 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1137 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1138 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1139 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1140 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1143 data = ast_mindwm(ast, 0x1E6E001C);
1145 data = ast_mindwm(ast, 0x1E6E001C);
1148 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1152 ast_moutdwm(ast, 0x1E6E0064, data2);
1158 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1161 ast_moutdwm(ast, 0x1E6E0068, data);
1163 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1165 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1166 ast_moutdwm(ast, 0x1E6E0018, data);
1168 ast_moutdwm(ast, 0x1E6E0018, data);
1170 data = ast_mindwm(ast, 0x1E6E001C);
1173 data = ast_mindwm(ast, 0x1E6E001C);
1176 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1177 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1178 ast_moutdwm(ast, 0x1E6E0018, data);
1180 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1181 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1184 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1185 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1186 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1187 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1188 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1189 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1190 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1191 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1192 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1194 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1202 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1205 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1208 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1211 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1212 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1214 data = ast_mindwm(ast, 0x1E6E0070);
1216 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1217 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1218 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1224 static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param)
1228 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1231 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1245 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1260 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1291 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1325 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1358 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1373 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1389 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1405 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1421 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1471 static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1476 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1477 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1478 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1479 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1480 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1482 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1485 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1486 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1487 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1488 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1489 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1490 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1491 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1492 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1493 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1494 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1495 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1496 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1497 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1498 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1499 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1500 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1501 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1502 ast_moutdwm(ast, 0x1E6E0054, 0);
1503 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1504 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1505 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1506 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1507 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1508 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1512 data = ast_mindwm(ast, 0x1E6E001C);
1514 data = ast_mindwm(ast, 0x1E6E001C);
1517 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1521 ast_moutdwm(ast, 0x1E6E0064, data2);
1527 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1530 ast_moutdwm(ast, 0x1E6E0068, data);
1532 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1534 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1535 ast_moutdwm(ast, 0x1E6E0018, data);
1537 ast_moutdwm(ast, 0x1E6E0018, data);
1539 data = ast_mindwm(ast, 0x1E6E001C);
1542 data = ast_mindwm(ast, 0x1E6E001C);
1545 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1546 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1547 ast_moutdwm(ast, 0x1E6E0018, data);
1549 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1550 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1553 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1554 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1555 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1556 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1557 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1558 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1560 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1561 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1562 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1563 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1564 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1565 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1566 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1568 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1576 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1577 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1580 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1585 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1586 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1588 data = ast_mindwm(ast, 0x1E6E0070);
1590 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1591 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1592 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1599 struct ast_private *ast = to_ast_private(dev);
1604 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1606 ast_write32(ast, 0xf004, 0x1e6e0000);
1607 ast_write32(ast, 0xf000, 0x1);
1608 ast_write32(ast, 0x12000, 0x1688a8a8);
1611 } while (ast_read32(ast, 0x12000) != 0x1);
1613 ast_write32(ast, 0x10000, 0xfc600309);
1616 } while (ast_read32(ast, 0x10000) != 0x1);
1619 temp = ast_read32(ast, 0x12008);
1621 ast_write32(ast, 0x12008, temp);
1625 temp = ast_mindwm(ast, 0x1e6e2070);
1663 get_ddr3_info(ast, ¶m);
1664 ddr3_init(ast, ¶m);
1666 get_ddr2_info(ast, ¶m);
1667 ddr2_init(ast, ¶m);
1670 temp = ast_mindwm(ast, 0x1e6e2040);
1671 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1676 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1680 static bool cbr_test_2500(struct ast_private *ast)
1682 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1683 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1684 if (!mmc_test_burst(ast, 0))
1686 if (!mmc_test_single_2500(ast, 0))
1691 static bool ddr_test_2500(struct ast_private *ast)
1693 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1694 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1695 if (!mmc_test_burst(ast, 0))
1697 if (!mmc_test_burst(ast, 1))
1699 if (!mmc_test_burst(ast, 2))
1701 if (!mmc_test_burst(ast, 3))
1703 if (!mmc_test_single_2500(ast, 0))
1708 static void ddr_init_common_2500(struct ast_private *ast)
1710 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1711 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1712 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1713 ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1714 ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1715 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1716 ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1717 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1718 ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1719 ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1720 ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1721 ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1722 ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1723 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1724 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1725 ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1726 ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1727 ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1728 ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1731 static void ddr_phy_init_2500(struct ast_private *ast)
1736 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1739 data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1744 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1749 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1751 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1755 ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1765 static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)
1769 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1770 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1772 ast_moutdwm(ast, 0xA0100000, 0x41424344);
1773 ast_moutdwm(ast, 0x90100000, 0x35363738);
1774 ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1775 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1778 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1782 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1786 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1792 ast_moutdwm(ast, 0x1E6E0004, reg_04);
1793 ast_moutdwm(ast, 0x1E6E0014, reg_14);
1796 static void enable_cache_2500(struct ast_private *ast)
1800 reg_04 = ast_mindwm(ast, 0x1E6E0004);
1801 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1804 data = ast_mindwm(ast, 0x1E6E0004);
1806 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1809 static void set_mpll_2500(struct ast_private *ast)
1814 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1815 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1817 ast_moutdwm(ast, addr, 0x0);
1820 ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1822 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1823 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1827 ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1832 ast_moutdwm(ast, 0x1E6E2020, param);
1836 static void reset_mmc_2500(struct ast_private *ast)
1838 ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1839 ast_moutdwm(ast, 0x1E785044, 0x00000001);
1840 ast_moutdwm(ast, 0x1E785048, 0x00004755);
1841 ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1843 ast_moutdwm(ast, 0x1E785054, 0x00000077);
1844 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1847 static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
1850 ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1851 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1852 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1853 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1854 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1855 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1856 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1857 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1860 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1861 ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1862 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1863 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1864 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1865 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1866 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1867 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1868 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1869 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1870 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1871 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1872 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1873 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1876 ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1879 ddr_phy_init_2500(ast);
1881 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1882 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1883 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1885 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1886 enable_cache_2500(ast);
1887 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1888 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1891 static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)
1898 ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1899 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1900 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1901 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1902 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1903 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1904 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1905 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1908 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1909 ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1910 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1911 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1912 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1913 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1914 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1915 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1916 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1917 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1918 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1919 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1920 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1921 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1922 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1925 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1933 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1935 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1936 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1937 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1939 ddr_phy_init_2500(ast);
1940 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1941 if (cbr_test_2500(ast)) {
1943 data = ast_mindwm(ast, 0x1E6E03D0);
1956 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1966 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1967 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1968 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1970 ddr_phy_init_2500(ast);
1971 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1972 if (cbr_test_2500(ast)) {
1983 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1984 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1986 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1989 ddr_phy_init_2500(ast);
1991 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1992 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1993 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1995 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1996 enable_cache_2500(ast);
1997 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1998 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
2001 static bool ast_dram_init_2500(struct ast_private *ast)
2009 set_mpll_2500(ast);
2010 reset_mmc_2500(ast);
2011 ddr_init_common_2500(ast);
2013 data = ast_mindwm(ast, 0x1E6E2070);
2015 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
2017 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
2018 } while (!ddr_test_2500(ast));
2020 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
2023 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
2024 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
2031 struct ast_private *ast = to_ast_private(dev);
2035 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
2038 ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
2039 ast_moutdwm(ast, 0x1e600084, 0x00010000);
2040 ast_moutdwm(ast, 0x1e600088, 0x00000000);
2041 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
2042 ast_write32(ast, 0xf004, 0x1e6e0000);
2043 ast_write32(ast, 0xf000, 0x1);
2044 ast_write32(ast, 0x12000, 0x1688a8a8);
2045 while (ast_read32(ast, 0x12000) != 0x1)
2048 ast_write32(ast, 0x10000, 0xfc600309);
2049 while (ast_read32(ast, 0x10000) != 0x1)
2053 temp = ast_read32(ast, 0x12008);
2055 ast_write32(ast, 0x12008, temp);
2058 ast_moutdwm(ast, 0x1e6e2090, 0x20000000);
2059 temp = ast_mindwm(ast, 0x1e6e2094);
2061 ast_moutdwm(ast, 0x1e6e2094, temp);
2062 temp = ast_mindwm(ast, 0x1e6e2070);
2064 ast_moutdwm(ast, 0x1e6e207c, 0x00800000);
2066 ast_moutdwm(ast, 0x1e6e2070, 0x00800000);
2069 if (!ast_dram_init_2500(ast))
2072 temp = ast_mindwm(ast, 0x1e6e2040);
2073 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
2078 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);