Lines Matching refs:ast
13 struct ast_private *ast = data;
15 release_firmware(ast->dp501_fw);
16 ast->dp501_fw = NULL;
21 struct ast_private *ast = to_ast_private(dev);
24 ret = request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev);
28 return devm_add_action_or_reset(dev->dev, ast_release_firmware, ast);
31 static void send_ack(struct ast_private *ast)
34 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
39 static void send_nack(struct ast_private *ast)
42 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
44 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
47 static bool wait_ack(struct ast_private *ast)
52 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
63 static bool wait_nack(struct ast_private *ast)
68 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
79 static void set_cmd_trigger(struct ast_private *ast)
81 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40);
84 static void clear_cmd_trigger(struct ast_private *ast)
86 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00);
90 static bool wait_fw_ready(struct ast_private *ast)
95 waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
109 struct ast_private *ast = to_ast_private(dev);
111 if (wait_nack(ast)) {
112 send_nack(ast);
113 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
114 send_ack(ast);
115 set_cmd_trigger(ast);
117 if (wait_ack(ast)) {
118 clear_cmd_trigger(ast);
119 send_nack(ast);
124 clear_cmd_trigger(ast);
125 send_nack(ast);
131 struct ast_private *ast = to_ast_private(dev);
133 if (wait_nack(ast)) {
134 send_nack(ast);
135 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
136 send_ack(ast);
137 if (wait_ack(ast)) {
138 send_nack(ast);
142 send_nack(ast);
149 struct ast_private *ast = to_ast_private(dev);
154 if (wait_ack(ast) == false)
156 tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff);
158 if (wait_nack(ast) == false) {
159 send_nack(ast);
162 send_nack(ast);
166 static void clear_cmd(struct ast_private *ast)
168 send_nack(ast);
169 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
181 static u32 get_fw_base(struct ast_private *ast)
183 return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff;
188 struct ast_private *ast = to_ast_private(dev);
192 if (ast->config_mode != ast_use_p2a)
195 data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
197 boot_address = get_fw_base(ast);
199 *(u32 *)(addr + i) = ast_mindwm(ast, boot_address + i);
207 struct ast_private *ast = to_ast_private(dev);
213 if (ast->config_mode != ast_use_p2a)
216 data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
219 if (ast->dp501_fw_addr) {
220 fw_addr = ast->dp501_fw_addr;
223 if (!ast->dp501_fw &&
227 fw_addr = (u8 *)ast->dp501_fw->data;
228 len = ast->dp501_fw->size;
231 ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
232 data = ast_mindwm(ast, 0x1e6e0004);
253 ast_moutdwm(ast, boot_address + i, data);
257 ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
260 ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address);
261 ast_moutdwm(ast, 0x1e6e2100, 1);
264 data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff; /* D[11:9] = 100b: UEFI handling */
266 ast_moutdwm(ast, 0x1e6e2040, data);
268 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */
270 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg);
277 struct ast_private *ast = to_ast_private(dev);
282 if (ast->config_mode == ast_use_p2a) {
283 boot_address = get_fw_base(ast);
287 data = ast_mindwm(ast, boot_address + offset);
294 *plinkcap = ast_mindwm(ast, boot_address + offset);
304 if (!ast->dp501_fw_buf)
309 data = readl(ast->dp501_fw_buf + offset);
313 data = readl(ast->dp501_fw_buf + offset);
320 *plinkcap = readl(ast->dp501_fw_buf + offset);
335 struct ast_private *ast = to_ast_private(dev);
339 if (ast->config_mode == ast_use_p2a) {
340 boot_address = get_fw_base(ast);
344 data = ast_mindwm(ast, boot_address + offset);
350 data = ast_mindwm(ast, boot_address + offset);
357 data = ast_mindwm(ast, boot_address + offset + i);
362 if (!ast->dp501_fw_buf)
367 data = readl(ast->dp501_fw_buf + offset);
371 data = readl(ast->dp501_fw_buf + offset);
377 data = readl(ast->dp501_fw_buf + offset);
384 data = readl(ast->dp501_fw_buf + offset + i);
395 struct ast_private *ast = to_ast_private(dev);
398 ast_write32(ast, 0xf004, 0x1e6e0000);
399 ast_write32(ast, 0xf000, 0x1);
400 ast_write32(ast, 0x12000, 0x1688a8a8);
402 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
405 data = ast_read32(ast, 0x12008);
409 ast_write32(ast, 0x12008, data);
411 if (ast->chip == AST2300) {
412 data = ast_read32(ast, 0x12084);
415 ast_write32(ast, 0x12084, data);
417 data = ast_read32(ast, 0x12088);
420 ast_write32(ast, 0x12088, data);
422 data = ast_read32(ast, 0x12090);
426 ast_write32(ast, 0x12090, data);
428 data = ast_read32(ast, 0x12088);
431 ast_write32(ast, 0x12088, data);
433 data = ast_read32(ast, 0x1208c);
436 ast_write32(ast, 0x1208c, data);
438 data = ast_read32(ast, 0x120a4);
441 ast_write32(ast, 0x120a4, data);
443 data = ast_read32(ast, 0x120a8);
446 ast_write32(ast, 0x120a8, data);
448 data = ast_read32(ast, 0x12094);
451 ast_write32(ast, 0x12094, data);
456 data = ast_read32(ast, 0x1202c);
458 ast_write32(ast, 0x1202c, data);
461 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
468 struct ast_private *ast = to_ast_private(dev);
476 ast_write32(ast, 0xf004, 0x1e6e0000);
477 ast_write32(ast, 0xf000, 0x1);
480 ast_write32(ast, 0x12000, 0x1688a8a8);
481 ast_write32(ast, 0x12000, 0x1688a8a8);
482 ast_write32(ast, 0x12000, 0x1688a8a8);
485 data = ast_read32(ast, 0x1202c);
487 ast_write32(ast, 0, data);
490 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00);
495 struct ast_private *ast = to_ast_private(dev);
498 if (ast->chip == AST2300 || ast->chip == AST2400) {
499 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
511 if (ast->tx_chip_type == AST_TX_SIL164)