Lines Matching refs:adj
200 const struct drm_display_mode *mode, struct drm_display_mode *adj)
210 drm_mode_set_crtcinfo(adj, CRTC_INTERLACE_HALVE_V);
216 if (armada_drm_crtc_mode_valid(crtc, adj) != MODE_OK)
220 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
332 struct drm_display_mode *adj = &crtc->state->adjusted_mode;
338 bool interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
341 rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
342 lm = adj->crtc_htotal - adj->crtc_hsync_end;
343 bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
344 tm = adj->crtc_vtotal - adj->crtc_vsync_end;
347 crtc->base.id, crtc->name, DRM_MODE_ARG(adj));
351 dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
359 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
360 adj->crtc_htotal;
362 val = adj->crtc_hsync_start;
367 val -= adj->crtc_htotal / 2;
376 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
389 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
401 if (adj->flags & DRM_MODE_FLAG_NCSYNC)
403 if (adj->flags & DRM_MODE_FLAG_NHSYNC)
405 if (adj->flags & DRM_MODE_FLAG_NVSYNC)