Lines Matching refs:hwdev
41 static void malidp_write_gamma_table(struct malidp_hw_device *hwdev,
52 malidp_hw_write(hwdev, gamma_write_mask,
53 hwdev->hw->map.coeffs_base + MALIDP_COEF_TABLE_ADDR);
55 malidp_hw_write(hwdev, data[i],
56 hwdev->hw->map.coeffs_base +
64 struct malidp_hw_device *hwdev = malidp->dev;
70 malidp_hw_clearbits(hwdev,
79 malidp_write_gamma_table(hwdev, mc->gamma_coeffs);
81 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_GAMMA,
91 struct malidp_hw_device *hwdev = malidp->dev;
98 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_CADJ,
107 malidp_hw_write(hwdev,
109 hwdev->hw->map.coeffs_base +
112 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ,
123 struct malidp_hw_device *hwdev = malidp->dev;
126 u32 se_control = hwdev->hw->map.se_base +
127 ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
135 val = malidp_hw_read(hwdev, se_control);
137 malidp_hw_write(hwdev, val, se_control);
141 hwdev->hw->se_set_scaling_coeffs(hwdev, s, old_s);
142 val = malidp_hw_read(hwdev, se_control);
149 malidp_hw_write(hwdev, val, se_control);
154 malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE);
157 malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE);
160 malidp_hw_write(hwdev, s->h_init_phase, scr + MALIDP_SE_H_INIT_PH);
161 malidp_hw_write(hwdev, s->h_delta_phase, scr + MALIDP_SE_H_DELTA_PH);
162 malidp_hw_write(hwdev, s->v_init_phase, scr + MALIDP_SE_V_INIT_PH);
163 malidp_hw_write(hwdev, s->v_delta_phase, scr + MALIDP_SE_V_DELTA_PH);
172 struct malidp_hw_device *hwdev = malidp->dev;
175 hwdev->hw->set_config_valid(hwdev, 1);
177 if (hwdev->hw->in_config_mode(hwdev)) {
393 struct malidp_hw_device *hwdev = malidp->dev;
397 drm->mode_config.min_width = hwdev->min_line_size;
398 drm->mode_config.min_height = hwdev->min_line_size;
399 drm->mode_config.max_width = hwdev->max_line_size;
400 drm->mode_config.max_height = hwdev->max_line_size;
430 struct malidp_hw_device *hwdev = malidp->dev;
450 malidp_de_irq_fini(hwdev);
595 static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev,
608 core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID);
621 core_id = malidp_hw_read(hwdev,
672 struct malidp_hw_device *hwdev = malidp->dev;
675 WARN_ON(!hwdev->hw->in_config_mode(hwdev));
677 malidp_se_irq_fini(hwdev);
678 malidp_de_irq_fini(hwdev);
679 hwdev->pm_suspended = true;
680 clk_disable_unprepare(hwdev->mclk);
681 clk_disable_unprepare(hwdev->aclk);
682 clk_disable_unprepare(hwdev->pclk);
691 struct malidp_hw_device *hwdev = malidp->dev;
693 clk_prepare_enable(hwdev->pclk);
694 clk_prepare_enable(hwdev->aclk);
695 clk_prepare_enable(hwdev->mclk);
696 hwdev->pm_suspended = false;
697 malidp_de_irq_hw_init(hwdev);
698 malidp_se_irq_hw_init(hwdev);
708 struct malidp_hw_device *hwdev;
721 hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL);
722 if (!hwdev)
725 hwdev->hw = (struct malidp_hw *)of_device_get_match_data(dev);
726 malidp->dev = hwdev;
729 hwdev->regs = devm_ioremap_resource(dev, res);
730 if (IS_ERR(hwdev->regs))
731 return PTR_ERR(hwdev->regs);
733 hwdev->pclk = devm_clk_get(dev, "pclk");
734 if (IS_ERR(hwdev->pclk))
735 return PTR_ERR(hwdev->pclk);
737 hwdev->aclk = devm_clk_get(dev, "aclk");
738 if (IS_ERR(hwdev->aclk))
739 return PTR_ERR(hwdev->aclk);
741 hwdev->mclk = devm_clk_get(dev, "mclk");
742 if (IS_ERR(hwdev->mclk))
743 return PTR_ERR(hwdev->mclk);
745 hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
746 if (IS_ERR(hwdev->pxlclk))
747 return PTR_ERR(hwdev->pxlclk);
784 if (!malidp_is_compatible_hw_id(hwdev, dev_id)) {
789 ret = hwdev->hw->query_hw(hwdev);
795 version = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_DE_CORE_ID);
803 &hwdev->arqos_value);
805 hwdev->arqos_value = 0x0;
816 malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base);
817 hwdev->output_color_depth = out_depth;
873 malidp_se_irq_fini(hwdev);
874 malidp_de_irq_fini(hwdev);
902 struct malidp_hw_device *hwdev = malidp->dev;
908 malidp_se_irq_fini(hwdev);
909 malidp_de_irq_fini(hwdev);