Lines Matching refs:hdlcd
41 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
44 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
50 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
51 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
53 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);
60 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
61 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
63 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
85 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
103 hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);
115 hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset |
120 hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset |
122 hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset |
130 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
150 hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
153 hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
154 hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
155 hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
156 hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
157 hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
158 hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
159 hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
160 hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
161 hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);
167 clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);
173 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
175 clk_prepare_enable(hdlcd->clk);
177 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
184 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
187 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
188 clk_disable_unprepare(hdlcd->clk);
194 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
197 rate = clk_round_rate(hdlcd->clk, clk_rate);
262 struct hdlcd_drm_private *hdlcd;
272 hdlcd = plane->dev->dev_private;
273 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);
274 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]);
275 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
276 hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
295 struct hdlcd_drm_private *hdlcd = drm->dev_private;
315 hdlcd->plane = plane;
322 struct hdlcd_drm_private *hdlcd = drm->dev_private;
330 ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL,
335 drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs);