Lines Matching refs:data
449 /* set index to data for continous read */
1418 uint32_t temp, data;
1420 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1423 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1427 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1431 if (temp != data)
1432 WREG32_PCIE(ixPCIE_CNTL2, data);
1438 uint32_t temp, data;
1440 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1443 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1445 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1447 if (temp != data)
1448 WREG32(mmHDP_HOST_PATH_CNTL, data);
1454 uint32_t temp, data;
1456 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1459 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1461 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1463 if (temp != data)
1464 WREG32(mmHDP_MEM_POWER_LS, data);
1470 uint32_t temp, data;
1472 temp = data = RREG32(0x157a);
1475 data |= 1;
1477 data &= ~1;
1479 if (temp != data)
1480 WREG32(0x157a, data);
1487 uint32_t temp, data;
1489 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1492 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1495 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1498 if (temp != data)
1499 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1670 int data;
1676 data = RREG32_PCIE(ixPCIE_CNTL2);
1677 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
1681 data = RREG32(mmHDP_MEM_POWER_LS);
1682 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1686 data = RREG32(mmHDP_HOST_PATH_CNTL);
1687 if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
1691 data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1692 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))