Lines Matching refs:adev
85 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
90 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
94 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
98 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
102 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
107 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
110 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
115 spin_lock_irqsave(&adev->smc_idx_lock, flags);
118 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
122 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
126 spin_lock_irqsave(&adev->smc_idx_lock, flags);
129 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
136 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
141 spin_lock_irqsave(&adev->smc_idx_lock, flags);
144 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
148 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
152 spin_lock_irqsave(&adev->smc_idx_lock, flags);
155 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
158 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
163 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
166 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
170 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
174 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
177 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
180 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
185 spin_lock_irqsave(&adev->didt_idx_lock, flags);
188 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
192 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
196 spin_lock_irqsave(&adev->didt_idx_lock, flags);
199 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
202 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
207 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
210 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
214 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
218 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
221 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
272 static void vi_init_golden_registers(struct amdgpu_device *adev)
275 mutex_lock(&adev->grbm_idx_mutex);
277 if (amdgpu_sriov_vf(adev)) {
278 xgpu_vi_init_golden_registers(adev);
279 mutex_unlock(&adev->grbm_idx_mutex);
283 switch (adev->asic_type) {
285 amdgpu_device_program_register_sequence(adev,
290 amdgpu_device_program_register_sequence(adev,
295 amdgpu_device_program_register_sequence(adev,
300 amdgpu_device_program_register_sequence(adev,
305 amdgpu_device_program_register_sequence(adev,
316 mutex_unlock(&adev->grbm_idx_mutex);
322 * @adev: amdgpu_device pointer
327 static u32 vi_get_xclk(struct amdgpu_device *adev)
329 u32 reference_clock = adev->clock.spll.reference_freq;
332 if (adev->flags & AMD_IS_APU) {
333 switch (adev->asic_type) {
356 * @adev: amdgpu_device pointer
366 void vi_srbm_select(struct amdgpu_device *adev,
377 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
382 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
392 if (adev->mode_info.num_crtc) {
401 if (adev->mode_info.num_crtc) {
414 r = amdgpu_read_bios(adev);
418 if (adev->mode_info.num_crtc) {
427 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
439 if (adev->flags & AMD_IS_APU)
445 spin_lock_irqsave(&adev->smc_idx_lock, flags);
453 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
537 static uint32_t vi_get_register_value(struct amdgpu_device *adev,
548 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
550 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
552 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
554 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
557 mutex_lock(&adev->grbm_idx_mutex);
559 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
564 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
565 mutex_unlock(&adev->grbm_idx_mutex);
572 return adev->gfx.config.gb_addr_config;
574 return adev->gfx.config.mc_arb_ramcfg;
608 return adev->gfx.config.tile_mode_array[idx];
626 return adev->gfx.config.macrotile_mode_array[idx];
633 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
645 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
652 static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
656 dev_info(adev->dev, "GPU pci config reset\n");
659 pci_clear_master(adev->pdev);
661 amdgpu_device_pci_config_reset(adev);
666 for (i = 0; i < adev->usec_timeout; i++) {
669 pci_set_master(adev->pdev);
670 adev->has_hw_reset = true;
681 * @adev: amdgpu_device pointer
687 static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
691 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
693 r = vi_gpu_pci_config_reset(adev);
695 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
700 static bool vi_asic_supports_baco(struct amdgpu_device *adev)
702 switch (adev->asic_type) {
709 return amdgpu_dpm_is_baco_supported(adev);
716 vi_asic_reset_method(struct amdgpu_device *adev)
725 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
728 switch (adev->asic_type) {
735 baco_reset = amdgpu_dpm_is_baco_supported(adev);
751 * @adev: amdgpu_device pointer
757 static int vi_asic_reset(struct amdgpu_device *adev)
761 if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
762 dev_info(adev->dev, "BACO reset\n");
763 r = amdgpu_dpm_baco_reset(adev);
765 dev_info(adev->dev, "PCI CONFIG reset\n");
766 r = vi_asic_pci_config_reset(adev);
772 static u32 vi_get_config_memsize(struct amdgpu_device *adev)
777 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
784 r = amdgpu_atombios_get_clock_dividers(adev,
792 if (adev->flags & AMD_IS_APU)
802 if (adev->flags & AMD_IS_APU) {
823 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
827 if (adev->flags & AMD_IS_APU) {
828 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
832 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
836 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
840 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
848 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
858 if (adev->flags & AMD_IS_APU) {
870 r = amdgpu_atombios_get_clock_dividers(adev,
902 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
904 if (pci_is_root_bus(adev->pdev->bus))
910 if (adev->flags & AMD_IS_APU)
913 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
920 static void vi_program_aspm(struct amdgpu_device *adev)
929 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
935 if (adev->flags & AMD_IS_APU)
951 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
953 if (adev->flags & AMD_IS_APU)
961 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
971 static void vi_invalidate_hdp(struct amdgpu_device *adev,
982 static bool vi_need_full_reset(struct amdgpu_device *adev)
984 switch (adev->asic_type) {
1003 static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1013 if (adev->flags & AMD_IS_APU)
1049 static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev)
1061 static bool vi_need_reset_on_init(struct amdgpu_device *adev)
1065 if (adev->flags & AMD_IS_APU)
1078 static void vi_pre_asic_init(struct amdgpu_device *adev)
1110 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1112 if (adev->flags & AMD_IS_APU) {
1113 adev->smc_rreg = &cz_smc_rreg;
1114 adev->smc_wreg = &cz_smc_wreg;
1116 adev->smc_rreg = &vi_smc_rreg;
1117 adev->smc_wreg = &vi_smc_wreg;
1119 adev->pcie_rreg = &vi_pcie_rreg;
1120 adev->pcie_wreg = &vi_pcie_wreg;
1121 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1122 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1123 adev->didt_rreg = &vi_didt_rreg;
1124 adev->didt_wreg = &vi_didt_wreg;
1125 adev->gc_cac_rreg = &vi_gc_cac_rreg;
1126 adev->gc_cac_wreg = &vi_gc_cac_wreg;
1128 adev->asic_funcs = &vi_asic_funcs;
1130 adev->rev_id = vi_get_rev_id(adev);
1131 adev->external_rev_id = 0xFF;
1132 switch (adev->asic_type) {
1134 adev->cg_flags = 0;
1135 adev->pg_flags = 0;
1136 adev->external_rev_id = 0x1;
1139 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1156 adev->pg_flags = 0;
1157 adev->external_rev_id = adev->rev_id + 0x3c;
1160 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1173 adev->pg_flags = 0;
1174 adev->external_rev_id = adev->rev_id + 0x14;
1177 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1196 adev->pg_flags = 0;
1197 adev->external_rev_id = adev->rev_id + 0x5A;
1200 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1219 adev->pg_flags = 0;
1220 adev->external_rev_id = adev->rev_id + 0x50;
1223 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1242 adev->pg_flags = 0;
1243 adev->external_rev_id = adev->rev_id + 0x64;
1246 adev->cg_flags = 0;
1266 adev->pg_flags = 0;
1267 adev->external_rev_id = adev->rev_id + 0x6E;
1270 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1286 adev->pg_flags = 0;
1287 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
1288 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |
1294 adev->external_rev_id = adev->rev_id + 0x1;
1297 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1311 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1317 adev->external_rev_id = adev->rev_id + 0x61;
1324 if (amdgpu_sriov_vf(adev)) {
1325 amdgpu_virt_init_setting(adev);
1326 xgpu_vi_mailbox_set_irq_funcs(adev);
1334 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1336 if (amdgpu_sriov_vf(adev))
1337 xgpu_vi_mailbox_get_irq(adev);
1344 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1346 if (amdgpu_sriov_vf(adev))
1347 xgpu_vi_mailbox_add_irq_id(adev);
1359 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1362 vi_init_golden_registers(adev);
1364 vi_pcie_gen3_enable(adev);
1366 vi_program_aspm(adev);
1368 vi_enable_doorbell_aperture(adev, true);
1375 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1378 vi_enable_doorbell_aperture(adev, false);
1380 if (amdgpu_sriov_vf(adev))
1381 xgpu_vi_mailbox_put_irq(adev);
1388 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1390 return vi_common_hw_fini(adev);
1395 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1397 return vi_common_hw_init(adev);
1415 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1422 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1435 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1442 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1451 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1458 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1467 static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1474 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1484 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1491 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1507 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1509 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1510 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1514 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1524 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1527 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1528 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1532 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1542 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1545 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1546 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1550 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1560 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1564 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1574 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1576 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1586 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1589 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1600 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1603 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1614 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1622 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1624 if (amdgpu_sriov_vf(adev))
1627 switch (adev->asic_type) {
1629 vi_update_bif_medium_grain_light_sleep(adev,
1631 vi_update_hdp_medium_grain_clock_gating(adev,
1633 vi_update_hdp_light_sleep(adev,
1635 vi_update_rom_medium_grain_clock_gating(adev,
1640 vi_update_bif_medium_grain_light_sleep(adev,
1642 vi_update_hdp_medium_grain_clock_gating(adev,
1644 vi_update_hdp_light_sleep(adev,
1646 vi_update_drm_light_sleep(adev,
1654 vi_common_set_clockgating_state_by_smu(adev, state);
1669 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1672 if (amdgpu_sriov_vf(adev))
1723 void vi_set_virt_ops(struct amdgpu_device *adev)
1725 adev->virt.ops = &xgpu_vi_virt_ops;
1728 int vi_set_ip_blocks(struct amdgpu_device *adev)
1730 switch (adev->asic_type) {
1733 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1734 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
1735 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
1736 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1737 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
1738 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1739 if (adev->enable_virtual_display)
1740 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1743 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1744 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
1745 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1746 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1747 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1748 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1749 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1750 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1752 else if (amdgpu_device_has_dc_support(adev))
1753 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1756 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
1757 if (!amdgpu_sriov_vf(adev)) {
1758 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1759 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1763 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1764 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1765 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1766 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1767 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1768 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1769 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1770 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1772 else if (amdgpu_device_has_dc_support(adev))
1773 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1776 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
1777 if (!amdgpu_sriov_vf(adev)) {
1778 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
1779 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1786 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1787 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
1788 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1789 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1790 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
1791 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1792 if (adev->enable_virtual_display)
1793 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1795 else if (amdgpu_device_has_dc_support(adev))
1796 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1799 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
1800 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
1801 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1804 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1805 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1806 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1807 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1808 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1809 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1810 if (adev->enable_virtual_display)
1811 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1813 else if (amdgpu_device_has_dc_support(adev))
1814 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1817 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1818 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1819 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
1821 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1825 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1826 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1827 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1828 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
1829 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1830 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1831 if (adev->enable_virtual_display)
1832 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1834 else if (amdgpu_device_has_dc_support(adev))
1835 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1838 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1839 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
1840 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1842 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1853 void legacy_doorbell_index_init(struct amdgpu_device *adev)
1855 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
1856 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
1857 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
1858 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
1859 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
1860 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
1861 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
1862 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
1863 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
1864 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
1865 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;
1866 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;
1867 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
1868 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;