Lines Matching refs:data
104 unsigned long address, data;
106 data = adev->nbio.funcs->get_pcie_data_offset(adev);
108 return amdgpu_device_indirect_rreg(adev, address, data, reg);
113 unsigned long address, data;
116 data = adev->nbio.funcs->get_pcie_data_offset(adev);
118 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
123 unsigned long address, data;
125 data = adev->nbio.funcs->get_pcie_data_offset(adev);
127 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
132 unsigned long address, data;
135 data = adev->nbio.funcs->get_pcie_data_offset(adev);
137 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
142 unsigned long flags, address, data;
146 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
150 r = RREG32(data);
157 unsigned long flags, address, data;
160 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
164 WREG32(data, (v));
170 unsigned long flags, address, data;
174 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
178 r = RREG32(data);
185 unsigned long flags, address, data;
188 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
192 WREG32(data, (v));
314 /* read out the rom data */
1435 uint32_t def, data;
1440 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1443 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1448 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1453 if (def != data)
1454 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1456 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1459 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1461 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1463 if (def != data)
1464 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1470 uint32_t def, data;
1472 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1475 data &= ~(0x01000000 |
1484 data |= (0x01000000 |
1493 if (def != data)
1494 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1499 uint32_t def, data;
1501 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1504 data |= 1;
1506 data &= ~1;
1508 if (def != data)
1509 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1515 uint32_t def, data;
1517 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1520 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1523 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1526 if (def != data)
1527 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1585 int data;
1593 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1594 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1598 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1599 if (!(data & 0x01000000))
1603 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1604 if (data & 0x1)
1608 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1609 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))