Lines Matching refs:data
2319 u32 data, orig;
2328 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
2329 data &= ~LC_XMIT_N_FTS_MASK;
2330 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
2331 if (orig != data)
2332 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
2334 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
2335 data |= LC_GO_TO_RECOVERY;
2336 if (orig != data)
2337 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
2339 orig = data = RREG32_PCIE(PCIE_P_CNTL);
2340 data |= P_IGNORE_EDB_ERR;
2341 if (orig != data)
2342 WREG32_PCIE(PCIE_P_CNTL, data);
2344 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
2345 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
2346 data |= LC_PMI_TO_L1_DIS;
2348 data |= LC_L0S_INACTIVITY(7);
2351 data |= LC_L1_INACTIVITY(7);
2352 data &= ~LC_PMI_TO_L1_DIS;
2353 if (orig != data)
2354 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
2359 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
2360 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
2361 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
2362 if (orig != data)
2363 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
2365 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
2366 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
2367 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
2368 if (orig != data)
2369 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
2371 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
2372 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
2373 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
2374 if (orig != data)
2375 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
2377 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
2378 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
2379 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
2380 if (orig != data)
2381 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
2384 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
2385 data &= ~PLL_RAMP_UP_TIME_0_MASK;
2386 if (orig != data)
2387 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
2389 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
2390 data &= ~PLL_RAMP_UP_TIME_1_MASK;
2391 if (orig != data)
2392 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
2394 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2);
2395 data &= ~PLL_RAMP_UP_TIME_2_MASK;
2396 if (orig != data)
2397 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data);
2399 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3);
2400 data &= ~PLL_RAMP_UP_TIME_3_MASK;
2401 if (orig != data)
2402 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data);
2404 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
2405 data &= ~PLL_RAMP_UP_TIME_0_MASK;
2406 if (orig != data)
2407 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
2409 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
2410 data &= ~PLL_RAMP_UP_TIME_1_MASK;
2411 if (orig != data)
2412 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
2414 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2);
2415 data &= ~PLL_RAMP_UP_TIME_2_MASK;
2416 if (orig != data)
2417 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data);
2419 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3);
2420 data &= ~PLL_RAMP_UP_TIME_3_MASK;
2421 if (orig != data)
2422 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
2424 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2425 data &= ~LC_DYN_LANES_PWR_STATE_MASK;
2426 data |= LC_DYN_LANES_PWR_STATE(3);
2427 if (orig != data)
2428 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
2430 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
2431 data &= ~LS2_EXIT_TIME_MASK;
2433 data |= LS2_EXIT_TIME(5);
2434 if (orig != data)
2435 si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
2437 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
2438 data &= ~LS2_EXIT_TIME_MASK;
2440 data |= LS2_EXIT_TIME(5);
2441 if (orig != data)
2442 si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
2458 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
2459 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
2460 if (orig != data)
2461 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
2463 orig = data = RREG32(THM_CLK_CNTL);
2464 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
2465 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
2466 if (orig != data)
2467 WREG32(THM_CLK_CNTL, data);
2469 orig = data = RREG32(MISC_CLK_CNTL);
2470 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
2471 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
2472 if (orig != data)
2473 WREG32(MISC_CLK_CNTL, data);
2475 orig = data = RREG32(CG_CLKPIN_CNTL);
2476 data &= ~BCLK_AS_XCLK;
2477 if (orig != data)
2478 WREG32(CG_CLKPIN_CNTL, data);
2480 orig = data = RREG32(CG_CLKPIN_CNTL_2);
2481 data &= ~FORCE_BIF_REFCLK_EN;
2482 if (orig != data)
2483 WREG32(CG_CLKPIN_CNTL_2, data);
2485 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
2486 data &= ~MPLL_CLKOUT_SEL_MASK;
2487 data |= MPLL_CLKOUT_SEL(4);
2488 if (orig != data)
2489 WREG32(MPLL_BYPASSCLK_SEL, data);
2491 orig = data = RREG32(SPLL_CNTL_MODE);
2492 data &= ~SPLL_REFCLK_SEL_MASK;
2493 if (orig != data)
2494 WREG32(SPLL_CNTL_MODE, data);
2498 if (orig != data)
2499 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
2502 orig = data = RREG32_PCIE(PCIE_CNTL2);
2503 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
2504 if (orig != data)
2505 WREG32_PCIE(PCIE_CNTL2, data);
2508 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
2509 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
2510 data = RREG32_PCIE(PCIE_LC_STATUS1);
2511 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
2512 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
2513 data &= ~LC_L0S_INACTIVITY_MASK;
2514 if (orig != data)
2515 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);