Lines Matching defs:vclk
1581 * @vclk: wanted VCLK
1591 * @optimal_vclk_div: resulting vclk post divider
1598 unsigned vclk, unsigned dclk,
1613 vco_min = max(max(vco_min, vclk), dclk);
1626 /* Calc vclk divider with current vco freq */
1627 vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk,
1639 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
1659 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1664 /* Bypass vclk and dclk with bclk */
1672 if (!vclk || !dclk) {
1677 r = si_calc_upll_dividers(adev, vclk, dclk, 125000, 250000,