Lines Matching refs:adev
70 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
73 address = adev->nbio.funcs->get_pcie_index_offset(adev);
74 data = adev->nbio.funcs->get_pcie_data_offset(adev);
76 return amdgpu_device_indirect_rreg(adev, address, data, reg);
79 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
83 address = adev->nbio.funcs->get_pcie_index_offset(adev);
84 data = adev->nbio.funcs->get_pcie_data_offset(adev);
86 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
89 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
92 address = adev->nbio.funcs->get_pcie_index_offset(adev);
93 data = adev->nbio.funcs->get_pcie_data_offset(adev);
95 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
98 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
102 address = adev->nbio.funcs->get_pcie_index_offset(adev);
103 data = adev->nbio.funcs->get_pcie_data_offset(adev);
105 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
108 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
116 spin_lock_irqsave(&adev->didt_idx_lock, flags);
119 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
123 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
130 spin_lock_irqsave(&adev->didt_idx_lock, flags);
133 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
136 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
138 return adev->nbio.funcs->get_memsize(adev);
141 static u32 nv_get_xclk(struct amdgpu_device *adev)
143 return adev->clock.spll.reference_freq;
147 void nv_grbm_select(struct amdgpu_device *adev,
159 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
164 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
170 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
181 if (adev->flags & AMD_IS_APU)
218 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
223 mutex_lock(&adev->grbm_idx_mutex);
225 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
230 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
231 mutex_unlock(&adev->grbm_idx_mutex);
235 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
240 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
243 return adev->gfx.config.gb_addr_config;
248 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
258 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
261 *value = nv_get_register_value(adev,
269 static int nv_asic_mode1_reset(struct amdgpu_device *adev)
274 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
277 pci_clear_master(adev->pdev);
279 amdgpu_device_cache_pci_state(adev->pdev);
281 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
282 dev_info(adev->dev, "GPU smu mode1 reset\n");
283 ret = amdgpu_dpm_mode1_reset(adev);
285 dev_info(adev->dev, "GPU psp mode1 reset\n");
286 ret = psp_gpu_reset(adev);
290 dev_err(adev->dev, "GPU mode1 reset failed\n");
291 amdgpu_device_load_pci_state(adev->pdev);
294 for (i = 0; i < adev->usec_timeout; i++) {
295 u32 memsize = adev->nbio.funcs->get_memsize(adev);
302 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
307 static bool nv_asic_supports_baco(struct amdgpu_device *adev)
309 struct smu_context *smu = &adev->smu;
318 nv_asic_reset_method(struct amdgpu_device *adev)
320 struct smu_context *smu = &adev->smu;
327 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
330 switch (adev->asic_type) {
342 static int nv_asic_reset(struct amdgpu_device *adev)
345 struct smu_context *smu = &adev->smu;
347 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
348 dev_info(adev->dev, "BACO reset\n");
357 dev_info(adev->dev, "MODE1 reset\n");
358 ret = nv_asic_mode1_reset(adev);
364 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
370 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
376 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
378 if (pci_is_root_bus(adev->pdev->bus))
384 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
391 static void nv_program_aspm(struct amdgpu_device *adev)
400 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
403 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
404 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
416 static int nv_reg_base_init(struct amdgpu_device *adev)
421 r = amdgpu_discovery_reg_base_init(adev);
432 switch (adev->asic_type) {
434 navi10_reg_base_init(adev);
437 navi14_reg_base_init(adev);
440 navi12_reg_base_init(adev);
444 sienna_cichlid_reg_base_init(adev);
453 void nv_set_virt_ops(struct amdgpu_device *adev)
455 adev->virt.ops = &xgpu_nv_virt_ops;
468 int nv_set_ip_blocks(struct amdgpu_device *adev)
472 adev->nbio.funcs = &nbio_v2_3_funcs;
473 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
475 if (adev->asic_type == CHIP_SIENNA_CICHLID)
476 adev->gmc.xgmi.supported = true;
479 r = nv_reg_base_init(adev);
483 switch (adev->asic_type) {
486 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
487 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
488 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
489 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
490 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
491 !amdgpu_sriov_vf(adev))
492 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
493 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
494 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
496 else if (amdgpu_device_has_dc_support(adev))
497 amdgpu_device_ip_block_add(adev, &dm_ip_block);
499 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
500 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
501 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
502 !amdgpu_sriov_vf(adev))
503 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
504 if (!nv_is_headless_sku(adev->pdev))
505 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
506 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
507 if (adev->enable_mes)
508 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
511 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
512 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
513 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
514 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
515 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
516 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
517 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
518 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
520 else if (amdgpu_device_has_dc_support(adev))
521 amdgpu_device_ip_block_add(adev, &dm_ip_block);
523 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
524 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
525 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
526 !amdgpu_sriov_vf(adev))
527 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
528 if (!nv_is_headless_sku(adev->pdev))
529 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
530 if (!amdgpu_sriov_vf(adev))
531 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
534 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
535 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
536 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
537 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
538 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
539 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
540 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
541 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
542 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
543 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
545 else if (amdgpu_device_has_dc_support(adev))
546 amdgpu_device_ip_block_add(adev, &dm_ip_block);
548 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
549 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
550 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
551 if (!amdgpu_sriov_vf(adev))
552 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
554 if (adev->enable_mes)
555 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
558 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
559 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
560 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
561 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
562 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
563 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
564 is_support_sw_smu(adev))
565 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
566 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
567 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
569 else if (amdgpu_device_has_dc_support(adev))
570 amdgpu_device_ip_block_add(adev, &dm_ip_block);
572 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
573 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
574 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
575 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
576 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
577 is_support_sw_smu(adev))
578 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
587 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
589 return adev->nbio.funcs->get_rev_id(adev);
592 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
594 adev->nbio.funcs->hdp_flush(adev, ring);
597 static void nv_invalidate_hdp(struct amdgpu_device *adev,
608 static bool nv_need_full_reset(struct amdgpu_device *adev)
613 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
617 if (adev->flags & AMD_IS_APU)
630 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
640 static void nv_init_doorbell_index(struct amdgpu_device *adev)
642 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
643 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
644 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
645 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
646 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
647 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
648 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
649 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
650 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
651 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
652 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
653 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
654 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
655 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
656 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
657 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
658 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
659 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
660 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
661 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
662 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
663 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
664 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
665 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
666 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
668 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
669 adev->doorbell_index.sdma_doorbell_range = 20;
672 static void nv_pre_asic_init(struct amdgpu_device *adev)
701 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
703 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
704 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
705 adev->smc_rreg = NULL;
706 adev->smc_wreg = NULL;
707 adev->pcie_rreg = &nv_pcie_rreg;
708 adev->pcie_wreg = &nv_pcie_wreg;
709 adev->pcie_rreg64 = &nv_pcie_rreg64;
710 adev->pcie_wreg64 = &nv_pcie_wreg64;
713 adev->uvd_ctx_rreg = NULL;
714 adev->uvd_ctx_wreg = NULL;
716 adev->didt_rreg = &nv_didt_rreg;
717 adev->didt_wreg = &nv_didt_wreg;
719 adev->asic_funcs = &nv_asic_funcs;
721 adev->rev_id = nv_get_rev_id(adev);
722 adev->external_rev_id = 0xff;
723 switch (adev->asic_type) {
725 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
740 adev->pg_flags = AMD_PG_SUPPORT_VCN |
744 adev->external_rev_id = adev->rev_id + 0x1;
747 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
762 adev->pg_flags = AMD_PG_SUPPORT_VCN |
765 adev->external_rev_id = adev->rev_id + 20;
768 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
784 adev->pg_flags = AMD_PG_SUPPORT_VCN |
792 if (amdgpu_sriov_vf(adev))
793 adev->rev_id = 0;
794 adev->external_rev_id = adev->rev_id + 0xa;
797 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
807 adev->pg_flags = AMD_PG_SUPPORT_VCN |
812 if (amdgpu_sriov_vf(adev)) {
814 adev->cg_flags = 0;
815 adev->pg_flags = 0;
817 adev->external_rev_id = adev->rev_id + 0x28;
820 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
830 adev->pg_flags = AMD_PG_SUPPORT_VCN |
835 adev->external_rev_id = adev->rev_id + 0x32;
843 if (amdgpu_sriov_vf(adev)) {
844 amdgpu_virt_init_setting(adev);
845 xgpu_nv_mailbox_set_irq_funcs(adev);
853 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
855 if (amdgpu_sriov_vf(adev))
856 xgpu_nv_mailbox_get_irq(adev);
863 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
865 if (amdgpu_sriov_vf(adev))
866 xgpu_nv_mailbox_add_irq_id(adev);
878 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
881 nv_pcie_gen3_enable(adev);
883 nv_program_aspm(adev);
885 adev->nbio.funcs->init_registers(adev);
890 if (adev->nbio.funcs->remap_hdp_registers)
891 adev->nbio.funcs->remap_hdp_registers(adev);
893 nv_enable_doorbell_aperture(adev, true);
900 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
903 nv_enable_doorbell_aperture(adev, false);
910 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
912 return nv_common_hw_fini(adev);
917 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
919 return nv_common_hw_init(adev);
937 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev,
943 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
980 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
987 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
994 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
1006 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
1020 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev,
1025 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1054 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1056 if (amdgpu_sriov_vf(adev))
1059 switch (adev->asic_type) {
1065 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1067 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1069 nv_update_hdp_mem_power_gating(adev,
1071 nv_update_hdp_clock_gating(adev,
1089 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1092 if (amdgpu_sriov_vf(adev))
1095 adev->nbio.funcs->get_clockgating_state(adev, flags);