Lines Matching refs:ws16c48gpio
55 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
59 if (ws16c48gpio->io_state[port] & mask)
67 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
72 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
74 ws16c48gpio->io_state[port] |= mask;
75 ws16c48gpio->out_state[port] &= ~mask;
76 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
78 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
86 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
91 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
93 ws16c48gpio->io_state[port] &= ~mask;
95 ws16c48gpio->out_state[port] |= mask;
97 ws16c48gpio->out_state[port] &= ~mask;
98 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
100 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
107 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
113 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
116 if (!(ws16c48gpio->io_state[port] & mask)) {
117 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
121 port_state = inb(ws16c48gpio->base + port);
123 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
131 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
141 port_addr = ws16c48gpio->base + offset / 8;
152 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
157 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
160 if (ws16c48gpio->io_state[port] & mask) {
161 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
166 ws16c48gpio->out_state[port] |= mask;
168 ws16c48gpio->out_state[port] &= ~mask;
169 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
171 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
177 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
187 port_addr = ws16c48gpio->base + index;
190 gpio_mask &= ~ws16c48gpio->io_state[index];
193 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
196 ws16c48gpio->out_state[index] &= ~gpio_mask;
197 ws16c48gpio->out_state[index] |= bitmask;
198 outb(ws16c48gpio->out_state[index], port_addr);
200 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
207 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
218 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
220 port_state = ws16c48gpio->irq_mask >> (8*port);
222 outb(0x80, ws16c48gpio->base + 7);
223 outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
224 outb(port_state | mask, ws16c48gpio->base + 8 + port);
225 outb(0xC0, ws16c48gpio->base + 7);
227 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
233 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
243 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
245 ws16c48gpio->irq_mask &= ~mask;
247 outb(0x80, ws16c48gpio->base + 7);
248 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
249 outb(0xC0, ws16c48gpio->base + 7);
251 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
257 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
267 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
269 ws16c48gpio->irq_mask |= mask;
271 outb(0x80, ws16c48gpio->base + 7);
272 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
273 outb(0xC0, ws16c48gpio->base + 7);
275 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
281 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
291 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
297 ws16c48gpio->flow_mask |= mask;
300 ws16c48gpio->flow_mask &= ~mask;
303 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
307 outb(0x40, ws16c48gpio->base + 7);
308 outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
309 outb(0xC0, ws16c48gpio->base + 7);
311 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
326 struct ws16c48_gpio *const ws16c48gpio = dev_id;
327 struct gpio_chip *const chip = &ws16c48gpio->chip;
333 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
340 int_id = inb(ws16c48gpio->base + 8 + port);
346 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
370 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc);
373 outb(0x80, ws16c48gpio->base + 7);
374 outb(0, ws16c48gpio->base + 8);
375 outb(0, ws16c48gpio->base + 9);
376 outb(0, ws16c48gpio->base + 10);
377 outb(0xC0, ws16c48gpio->base + 7);
384 struct ws16c48_gpio *ws16c48gpio;
389 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
390 if (!ws16c48gpio)
399 ws16c48gpio->chip.label = name;
400 ws16c48gpio->chip.parent = dev;
401 ws16c48gpio->chip.owner = THIS_MODULE;
402 ws16c48gpio->chip.base = -1;
403 ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
404 ws16c48gpio->chip.names = ws16c48_names;
405 ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
406 ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
407 ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
408 ws16c48gpio->chip.get = ws16c48_gpio_get;
409 ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
410 ws16c48gpio->chip.set = ws16c48_gpio_set;
411 ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
412 ws16c48gpio->base = base[id];
414 girq = &ws16c48gpio->chip.irq;
424 raw_spin_lock_init(&ws16c48gpio->lock);
426 err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
433 name, ws16c48gpio);