Lines Matching defs:wg
115 static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio)
127 if (wg->set_irq_mask)
128 regmap_update_bits(wg->regmap, reg, mask, mask);
130 regmap_update_bits(wg->regmap, reg, mask, 0);
133 static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio)
140 regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
145 struct wcove_gpio *wg = gpiochip_get_data(chip);
151 return regmap_write(wg->regmap, reg, CTLO_INPUT_SET);
157 struct wcove_gpio *wg = gpiochip_get_data(chip);
163 return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value);
168 struct wcove_gpio *wg = gpiochip_get_data(chip);
175 ret = regmap_read(wg->regmap, reg, &val);
187 struct wcove_gpio *wg = gpiochip_get_data(chip);
194 ret = regmap_read(wg->regmap, reg, &val);
203 struct wcove_gpio *wg = gpiochip_get_data(chip);
210 regmap_update_bits(wg->regmap, reg, 1, 1);
212 regmap_update_bits(wg->regmap, reg, 1, 0);
218 struct wcove_gpio *wg = gpiochip_get_data(chip);
226 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
229 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK,
241 struct wcove_gpio *wg = gpiochip_get_data(chip);
248 wg->intcnt = CTLI_INTCNT_DIS;
251 wg->intcnt = CTLI_INTCNT_BE;
254 wg->intcnt = CTLI_INTCNT_PE;
257 wg->intcnt = CTLI_INTCNT_NE;
263 wg->update |= UPDATE_IRQ_TYPE;
271 struct wcove_gpio *wg = gpiochip_get_data(chip);
273 mutex_lock(&wg->buslock);
279 struct wcove_gpio *wg = gpiochip_get_data(chip);
282 if (wg->update & UPDATE_IRQ_TYPE)
283 wcove_update_irq_ctrl(wg, gpio);
284 if (wg->update & UPDATE_IRQ_MASK)
285 wcove_update_irq_mask(wg, gpio);
286 wg->update = 0;
288 mutex_unlock(&wg->buslock);
294 struct wcove_gpio *wg = gpiochip_get_data(chip);
299 wg->set_irq_mask = false;
300 wg->update |= UPDATE_IRQ_MASK;
306 struct wcove_gpio *wg = gpiochip_get_data(chip);
311 wg->set_irq_mask = true;
312 wg->update |= UPDATE_IRQ_MASK;
326 struct wcove_gpio *wg = (struct wcove_gpio *)data;
330 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
331 dev_err(wg->dev, "Failed to read irq status register\n");
347 virq = irq_find_mapping(wg->chip.irq.domain, gpio);
349 regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
354 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
355 dev_err(wg->dev, "Failed to read irq status\n");
369 struct wcove_gpio *wg = gpiochip_get_data(chip);
374 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
375 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
376 ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group,
378 ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group,
400 struct wcove_gpio *wg;
422 wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
423 if (!wg)
426 wg->regmap_irq_chip = pmic->irq_chip_data;
428 platform_set_drvdata(pdev, wg);
430 mutex_init(&wg->buslock);
431 wg->chip.label = KBUILD_MODNAME;
432 wg->chip.direction_input = wcove_gpio_dir_in;
433 wg->chip.direction_output = wcove_gpio_dir_out;
434 wg->chip.get_direction = wcove_gpio_get_direction;
435 wg->chip.get = wcove_gpio_get;
436 wg->chip.set = wcove_gpio_set;
437 wg->chip.set_config = wcove_gpio_set_config,
438 wg->chip.base = -1;
439 wg->chip.ngpio = WCOVE_VGPIO_NUM;
440 wg->chip.can_sleep = true;
441 wg->chip.parent = pdev->dev.parent;
442 wg->chip.dbg_show = wcove_gpio_dbg_show;
443 wg->dev = dev;
444 wg->regmap = pmic->regmap;
446 virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
452 girq = &wg->chip.irq;
463 IRQF_ONESHOT, pdev->name, wg);
469 ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
476 ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
482 ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,