Lines Matching refs:val
60 unsigned int reg, u32 mask, u32 val)
68 tmp |= mask & val;
74 unsigned int reg, u32 mask, u32 val)
82 mask, val);
87 int val)
94 uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);
128 unsigned int offset, int val)
130 uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
142 unsigned int offset, int val)
144 uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val);
204 u32 val = 0;
207 val = mask;
211 uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val);
213 uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val);
429 u32 *val = priv->saved_vals;
436 *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
437 *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
440 *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN);
441 *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE);
442 *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
451 const u32 *val = priv->saved_vals;
458 writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
459 writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
462 writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN);
463 writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE);
464 writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);