Lines Matching defs:bit_cfg
78 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
80 return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0;
137 u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE;
147 bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
150 bit_cfg |= GPIO_BIT_CFG_TX_OD;
152 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
161 u64 bit_cfg;
171 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
173 if (bit_cfg & GPIO_BIT_CFG_TX_OE)
185 u64 bit_cfg;
201 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
238 bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK;
239 bit_cfg |= txgpio->line_entries[line].fil_bits;
240 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
253 (bit_cfg & GPIO_BIT_CFG_TX_OE))
332 u64 bit_cfg;
336 bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN;
340 bit_cfg |= GPIO_BIT_CFG_INT_TYPE;
347 bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
353 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
494 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));
504 txgpio->line_entries[i].fil_bits = bit_cfg ?
505 (bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS;
507 if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD))
509 if (bit_cfg & GPIO_BIT_CFG_PIN_XOR)