Lines Matching refs:port
107 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
110 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
231 unsigned int port;
240 port = GPIO_PORT(offset);
242 /* There is only one debounce count register per port and hence
245 spin_lock_irqsave(&bank->dbc_lock[port], flags);
246 if (bank->dbc_cnt[port] < debounce_ms) {
248 bank->dbc_cnt[port] = debounce_ms;
250 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
305 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
337 spin_lock_irqsave(&bank->lvl_lock[port], flags);
344 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
377 unsigned int port, pin, gpio;
387 for (port = 0; port < 4; port++) {
388 gpio = tegra_gpio_compose(bank->bank, port, 0);
494 u32 port, bit, mask;
501 port = GPIO_PORT(gpio);
506 bank->wake_enb[port] |= mask;
508 bank->wake_enb[port] &= ~mask;