Lines Matching refs:pl061
50 struct pl061 {
65 struct pl061 *pl061 = gpiochip_get_data(gc);
67 if (readb(pl061->base + GPIODIR) & BIT(offset))
75 struct pl061 *pl061 = gpiochip_get_data(gc);
79 raw_spin_lock_irqsave(&pl061->lock, flags);
80 gpiodir = readb(pl061->base + GPIODIR);
82 writeb(gpiodir, pl061->base + GPIODIR);
83 raw_spin_unlock_irqrestore(&pl061->lock, flags);
91 struct pl061 *pl061 = gpiochip_get_data(gc);
95 raw_spin_lock_irqsave(&pl061->lock, flags);
96 writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
97 gpiodir = readb(pl061->base + GPIODIR);
99 writeb(gpiodir, pl061->base + GPIODIR);
102 * gpio value is set again, because pl061 doesn't allow to set value of
105 writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
106 raw_spin_unlock_irqrestore(&pl061->lock, flags);
113 struct pl061 *pl061 = gpiochip_get_data(gc);
115 return !!readb(pl061->base + (BIT(offset + 2)));
120 struct pl061 *pl061 = gpiochip_get_data(gc);
122 writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
128 struct pl061 *pl061 = gpiochip_get_data(gc);
148 raw_spin_lock_irqsave(&pl061->lock, flags);
150 gpioiev = readb(pl061->base + GPIOIEV);
151 gpiois = readb(pl061->base + GPIOIS);
152 gpioibe = readb(pl061->base + GPIOIBE);
204 writeb(gpiois, pl061->base + GPIOIS);
205 writeb(gpioibe, pl061->base + GPIOIBE);
206 writeb(gpioiev, pl061->base + GPIOIEV);
208 raw_spin_unlock_irqrestore(&pl061->lock, flags);
218 struct pl061 *pl061 = gpiochip_get_data(gc);
223 pending = readb(pl061->base + GPIOMIS);
236 struct pl061 *pl061 = gpiochip_get_data(gc);
240 raw_spin_lock(&pl061->lock);
241 gpioie = readb(pl061->base + GPIOIE) & ~mask;
242 writeb(gpioie, pl061->base + GPIOIE);
243 raw_spin_unlock(&pl061->lock);
249 struct pl061 *pl061 = gpiochip_get_data(gc);
253 raw_spin_lock(&pl061->lock);
254 gpioie = readb(pl061->base + GPIOIE) | mask;
255 writeb(gpioie, pl061->base + GPIOIE);
256 raw_spin_unlock(&pl061->lock);
270 struct pl061 *pl061 = gpiochip_get_data(gc);
273 raw_spin_lock(&pl061->lock);
274 writeb(mask, pl061->base + GPIOIC);
275 raw_spin_unlock(&pl061->lock);
281 struct pl061 *pl061 = gpiochip_get_data(gc);
283 return irq_set_irq_wake(pl061->parent_irq, state);
289 struct pl061 *pl061;
293 pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
294 if (pl061 == NULL)
297 pl061->base = devm_ioremap_resource(dev, &adev->res);
298 if (IS_ERR(pl061->base))
299 return PTR_ERR(pl061->base);
301 raw_spin_lock_init(&pl061->lock);
302 pl061->gc.request = gpiochip_generic_request;
303 pl061->gc.free = gpiochip_generic_free;
304 pl061->gc.base = -1;
305 pl061->gc.get_direction = pl061_get_direction;
306 pl061->gc.direction_input = pl061_direction_input;
307 pl061->gc.direction_output = pl061_direction_output;
308 pl061->gc.get = pl061_get_value;
309 pl061->gc.set = pl061_set_value;
310 pl061->gc.ngpio = PL061_GPIO_NR;
311 pl061->gc.label = dev_name(dev);
312 pl061->gc.parent = dev;
313 pl061->gc.owner = THIS_MODULE;
318 pl061->irq_chip.name = dev_name(dev);
319 pl061->irq_chip.irq_ack = pl061_irq_ack;
320 pl061->irq_chip.irq_mask = pl061_irq_mask;
321 pl061->irq_chip.irq_unmask = pl061_irq_unmask;
322 pl061->irq_chip.irq_set_type = pl061_irq_type;
323 pl061->irq_chip.irq_set_wake = pl061_irq_set_wake;
325 writeb(0, pl061->base + GPIOIE); /* disable irqs */
329 pl061->parent_irq = irq;
331 girq = &pl061->gc.irq;
332 girq->chip = &pl061->irq_chip;
343 ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);
347 amba_set_drvdata(adev, pl061);
356 struct pl061 *pl061 = dev_get_drvdata(dev);
359 pl061->csave_regs.gpio_data = 0;
360 pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
361 pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
362 pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
363 pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
364 pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
367 if (pl061->csave_regs.gpio_dir & (BIT(offset)))
368 pl061->csave_regs.gpio_data |=
369 pl061_get_value(&pl061->gc, offset) << offset;
377 struct pl061 *pl061 = dev_get_drvdata(dev);
381 if (pl061->csave_regs.gpio_dir & (BIT(offset)))
382 pl061_direction_output(&pl061->gc, offset,
383 pl061->csave_regs.gpio_data &
386 pl061_direction_input(&pl061->gc, offset);
389 writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
390 writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
391 writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
392 writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);