Lines Matching defs:idio24gpio
144 struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
157 if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
166 struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
173 raw_spin_lock_irqsave(&idio24gpio->lock, flags);
176 ctl_state = ioread8(&idio24gpio->reg->ctl) & ~out_mode_mask;
177 iowrite8(ctl_state, &idio24gpio->reg->ctl);
179 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
188 struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
195 raw_spin_lock_irqsave(&idio24gpio->lock, flags);
198 ctl_state = ioread8(&idio24gpio->reg->ctl) | out_mode_mask;
199 iowrite8(ctl_state, &idio24gpio->reg->ctl);
201 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
210 struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
216 return !!(ioread8(&idio24gpio->reg->out0_7) & offset_mask);
219 return !!(ioread8(&idio24gpio->reg->out8_15) & offset_mask);
222 return !!(ioread8(&idio24gpio->reg->out16_23) & offset_mask);
226 return !!(ioread8(&idio24gpio->reg->in0_7) & offset_mask);
229 return !!(ioread8(&idio24gpio->reg->in8_15) & offset_mask);
232 return !!(ioread8(&idio24gpio->reg->in16_23) & offset_mask);
235 if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
236 return !!(ioread8(&idio24gpio->reg->ttl_out0_7) & offset_mask);
239 return !!(ioread8(&idio24gpio->reg->ttl_in0_7) & offset_mask);
245 struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
249 &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
250 &idio24gpio->reg->out16_23, &idio24gpio->reg->in0_7,
251 &idio24gpio->reg->in8_15, &idio24gpio->reg->in16_23,
266 else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
267 port_state = ioread8(&idio24gpio->reg->ttl_out0_7);
269 port_state = ioread8(&idio24gpio->reg->ttl_in0_7);
282 struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
294 if (offset > 47 && !(ioread8(&idio24gpio->reg->ctl) & out_mode_mask))
299 base = &idio24gpio->reg->ttl_out0_7;
302 base = &idio24gpio->reg->out16_23;
304 base = &idio24gpio->reg->out8_15;
306 base = &idio24gpio->reg->out0_7;
308 raw_spin_lock_irqsave(&idio24gpio->lock, flags);
317 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
323 struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
327 &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
328 &idio24gpio->reg->out16_23
341 raw_spin_lock_irqsave(&idio24gpio->lock, flags);
346 } else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) {
347 out_state = ioread8(&idio24gpio->reg->ttl_out0_7);
350 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
362 iowrite8(out_state, &idio24gpio->reg->ttl_out0_7);
364 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
375 struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
382 raw_spin_lock_irqsave(&idio24gpio->lock, flags);
384 idio24gpio->irq_mask &= ~BIT(bit_offset);
385 new_irq_mask = idio24gpio->irq_mask >> bank_offset * 8;
388 cos_enable_state = ioread8(&idio24gpio->reg->cos_enable);
395 iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable);
398 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
404 struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
411 raw_spin_lock_irqsave(&idio24gpio->lock, flags);
413 prev_irq_mask = idio24gpio->irq_mask >> bank_offset * 8;
414 idio24gpio->irq_mask |= BIT(bit_offset);
417 cos_enable_state = ioread8(&idio24gpio->reg->cos_enable);
424 iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable);
427 raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
450 struct idio_24_gpio *const idio24gpio = dev_id;
452 struct gpio_chip *const chip = &idio24gpio->chip;
456 raw_spin_lock(&idio24gpio->lock);
459 irq_status = ioread32(&idio24gpio->reg->cos0_7);
461 raw_spin_unlock(&idio24gpio->lock);
468 irq_mask = idio24gpio->irq_mask & irq_status;
474 raw_spin_lock(&idio24gpio->lock);
477 iowrite32(irq_status, &idio24gpio->reg->cos0_7);
479 raw_spin_unlock(&idio24gpio->lock);
498 struct idio_24_gpio *idio24gpio;
505 idio24gpio = devm_kzalloc(dev, sizeof(*idio24gpio), GFP_KERNEL);
506 if (!idio24gpio)
521 idio24gpio->plx = pcim_iomap_table(pdev)[pci_plx_bar_index];
522 idio24gpio->reg = pcim_iomap_table(pdev)[pci_bar_index];
524 idio24gpio->chip.label = name;
525 idio24gpio->chip.parent = dev;
526 idio24gpio->chip.owner = THIS_MODULE;
527 idio24gpio->chip.base = -1;
528 idio24gpio->chip.ngpio = IDIO_24_NGPIO;
529 idio24gpio->chip.names = idio_24_names;
530 idio24gpio->chip.get_direction = idio_24_gpio_get_direction;
531 idio24gpio->chip.direction_input = idio_24_gpio_direction_input;
532 idio24gpio->chip.direction_output = idio_24_gpio_direction_output;
533 idio24gpio->chip.get = idio_24_gpio_get;
534 idio24gpio->chip.get_multiple = idio_24_gpio_get_multiple;
535 idio24gpio->chip.set = idio_24_gpio_set;
536 idio24gpio->chip.set_multiple = idio_24_gpio_set_multiple;
538 girq = &idio24gpio->chip.irq;
547 raw_spin_lock_init(&idio24gpio->lock);
550 iowrite8(0, &idio24gpio->reg->soft_reset);
556 idio24gpio->plx + PLX_PEX8311_PCI_LCS_INTCSR + 1);
558 err = devm_gpiochip_add_data(dev, &idio24gpio->chip, idio24gpio);
565 name, idio24gpio);