Lines Matching refs:chip
101 struct pch_gpio *chip = gpiochip_get_data(gpio);
104 spin_lock_irqsave(&chip->spinlock, flags);
105 reg_val = ioread32(&chip->reg->po);
111 iowrite32(reg_val, &chip->reg->po);
112 spin_unlock_irqrestore(&chip->spinlock, flags);
117 struct pch_gpio *chip = gpiochip_get_data(gpio);
119 return !!(ioread32(&chip->reg->pi) & BIT(nr));
125 struct pch_gpio *chip = gpiochip_get_data(gpio);
130 spin_lock_irqsave(&chip->spinlock, flags);
132 reg_val = ioread32(&chip->reg->po);
137 iowrite32(reg_val, &chip->reg->po);
139 pm = ioread32(&chip->reg->pm);
140 pm &= BIT(gpio_pins[chip->ioh]) - 1;
142 iowrite32(pm, &chip->reg->pm);
144 spin_unlock_irqrestore(&chip->spinlock, flags);
151 struct pch_gpio *chip = gpiochip_get_data(gpio);
155 spin_lock_irqsave(&chip->spinlock, flags);
156 pm = ioread32(&chip->reg->pm);
157 pm &= BIT(gpio_pins[chip->ioh]) - 1;
159 iowrite32(pm, &chip->reg->pm);
160 spin_unlock_irqrestore(&chip->spinlock, flags);
168 static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
170 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
171 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
172 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
173 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
174 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
175 if (chip->ioh == INTEL_EG20T_PCH)
176 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
177 if (chip->ioh == OKISEMI_ML7223n_IOH)
178 chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
184 static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
186 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
187 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
189 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
191 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
192 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
193 if (chip->ioh == INTEL_EG20T_PCH)
194 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
195 if (chip->ioh == OKISEMI_ML7223n_IOH)
196 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
201 struct pch_gpio *chip = gpiochip_get_data(gpio);
203 return chip->irq_base + offset;
206 static void pch_gpio_setup(struct pch_gpio *chip)
208 struct gpio_chip *gpio = &chip->gpio;
210 gpio->label = dev_name(chip->dev);
211 gpio->parent = chip->dev;
218 gpio->ngpio = gpio_pins[chip->ioh];
226 struct pch_gpio *chip = gc->private;
232 ch = irq - chip->irq_base;
233 if (irq < chip->irq_base + 8) {
234 im_reg = &chip->reg->im0;
237 im_reg = &chip->reg->im1;
240 dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
262 spin_lock_irqsave(&chip->spinlock, flags);
274 spin_unlock_irqrestore(&chip->spinlock, flags);
281 struct pch_gpio *chip = gc->private;
283 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
289 struct pch_gpio *chip = gc->private;
291 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
297 struct pch_gpio *chip = gc->private;
299 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
304 struct pch_gpio *chip = dev_id;
305 unsigned long reg_val = ioread32(&chip->reg->istatus);
308 dev_vdbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val);
310 reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
312 for_each_set_bit(i, ®_val, gpio_pins[chip->ioh])
313 generic_handle_irq(chip->irq_base + i);
318 static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
326 gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
327 chip->base, handle_simple_irq);
331 gc->private = chip;
334 ct->chip.irq_ack = pch_irq_ack;
335 ct->chip.irq_mask = pch_irq_mask;
336 ct->chip.irq_unmask = pch_irq_unmask;
337 ct->chip.irq_set_type = pch_irq_type;
339 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
350 struct pch_gpio *chip;
353 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
354 if (chip == NULL)
357 chip->dev = &pdev->dev;
370 chip->base = pcim_iomap_table(pdev)[1];
373 chip->ioh = INTEL_EG20T_PCH;
375 chip->ioh = OKISEMI_ML7223m_IOH;
377 chip->ioh = OKISEMI_ML7223n_IOH;
379 chip->reg = chip->base;
380 pci_set_drvdata(pdev, chip);
381 spin_lock_init(&chip->spinlock);
382 pch_gpio_setup(chip);
384 ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip);
391 gpio_pins[chip->ioh], NUMA_NO_NODE);
394 chip->irq_base = -1;
397 chip->irq_base = irq_base;
400 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
401 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
404 IRQF_SHARED, KBUILD_MODNAME, chip);
410 return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
415 struct pch_gpio *chip = dev_get_drvdata(dev);
418 spin_lock_irqsave(&chip->spinlock, flags);
419 pch_gpio_save_reg_conf(chip);
420 spin_unlock_irqrestore(&chip->spinlock, flags);
427 struct pch_gpio *chip = dev_get_drvdata(dev);
430 spin_lock_irqsave(&chip->spinlock, flags);
431 iowrite32(0x01, &chip->reg->reset);
432 iowrite32(0x00, &chip->reg->reset);
433 pch_gpio_restore_reg_conf(chip);
434 spin_unlock_irqrestore(&chip->spinlock, flags);