Lines Matching refs:bank
77 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
83 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
108 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
111 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
117 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
120 void __iomem *reg = bank->base;
124 reg += bank->regs->set_dataout;
125 bank->context.dataout |= l;
127 reg += bank->regs->clr_dataout;
128 bank->context.dataout &= ~l;
135 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
138 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
142 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
144 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
145 clk_enable(bank->dbck);
146 bank->dbck_enabled = true;
148 writel_relaxed(bank->dbck_enable_mask,
149 bank->base + bank->regs->debounce_en);
153 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
155 if (bank->dbck_enable_mask && bank->dbck_enabled) {
161 writel_relaxed(0, bank->base + bank->regs->debounce_en);
163 clk_disable(bank->dbck);
164 bank->dbck_enabled = false;
170 * @bank: the gpio bank we're acting upon
171 * @offset: the gpio number on this @bank
180 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
187 if (!bank->dbck_flag)
198 clk_enable(bank->dbck);
199 writel_relaxed(debounce, bank->base + bank->regs->debounce);
201 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
202 bank->dbck_enable_mask = val;
204 clk_disable(bank->dbck);
213 omap_gpio_dbck_enable(bank);
214 if (bank->dbck_enable_mask) {
215 bank->context.debounce = debounce;
216 bank->context.debounce_en = val;
224 * @bank: the gpio bank we're acting upon
225 * @offset: the gpio number on this @bank
228 * this is the only gpio in this bank using debounce, then clear the debounce
230 * if this is the only gpio in the bank using debounce.
232 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
236 if (!bank->dbck_flag)
239 if (!(bank->dbck_enable_mask & gpio_bit))
242 bank->dbck_enable_mask &= ~gpio_bit;
243 bank->context.debounce_en &= ~gpio_bit;
244 writel_relaxed(bank->context.debounce_en,
245 bank->base + bank->regs->debounce_en);
247 if (!bank->dbck_enable_mask) {
248 bank->context.debounce = 0;
249 writel_relaxed(bank->context.debounce, bank->base +
250 bank->regs->debounce);
251 clk_disable(bank->dbck);
252 bank->dbck_enabled = false;
257 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
259 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
262 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
264 u32 no_wake = bank->non_wakeup_gpios;
272 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
275 void __iomem *base = bank->base;
278 omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
280 omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
288 omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
290 omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
293 bank->context.leveldetect0 =
294 readl_relaxed(bank->base + bank->regs->leveldetect0);
295 bank->context.leveldetect1 =
296 readl_relaxed(bank->base + bank->regs->leveldetect1);
297 bank->context.risingdetect =
298 readl_relaxed(bank->base + bank->regs->risingdetect);
299 bank->context.fallingdetect =
300 readl_relaxed(bank->base + bank->regs->fallingdetect);
302 bank->level_mask = bank->context.leveldetect0 |
303 bank->context.leveldetect1;
306 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
314 bank->enabled_non_wakeup_gpios |= gpio_bit;
316 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
324 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
326 if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {
327 void __iomem *reg = bank->base + bank->regs->irqctrl;
333 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
336 void __iomem *reg = bank->base;
339 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
340 omap_set_gpio_trigger(bank, gpio, trigger);
341 } else if (bank->regs->irqctrl) {
342 reg += bank->regs->irqctrl;
346 bank->toggle_mask |= BIT(gpio);
355 } else if (bank->regs->edgectrl1) {
357 reg += bank->regs->edgectrl2;
359 reg += bank->regs->edgectrl1;
373 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
375 if (bank->regs->pinctrl) {
376 void __iomem *reg = bank->base + bank->regs->pinctrl;
382 if (bank->regs->ctrl && !BANK_USED(bank)) {
383 void __iomem *reg = bank->base + bank->regs->ctrl;
390 bank->context.ctrl = ctrl;
394 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
396 if (bank->regs->ctrl && !BANK_USED(bank)) {
397 void __iomem *reg = bank->base + bank->regs->ctrl;
404 bank->context.ctrl = ctrl;
408 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
410 void __iomem *reg = bank->base + bank->regs->direction;
415 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
417 if (!LINE_USED(bank->mod_usage, offset)) {
418 omap_enable_gpio_module(bank, offset);
419 omap_set_gpio_direction(bank, offset, 1);
421 bank->irq_usage |= BIT(offset);
426 struct gpio_bank *bank = omap_irq_data_get_bank(d);
434 if (!bank->regs->leveldetect0 &&
438 raw_spin_lock_irqsave(&bank->lock, flags);
439 retval = omap_set_gpio_triggering(bank, offset, type);
441 raw_spin_unlock_irqrestore(&bank->lock, flags);
444 omap_gpio_init_irq(bank, offset);
445 if (!omap_gpio_is_input(bank, offset)) {
446 raw_spin_unlock_irqrestore(&bank->lock, flags);
450 raw_spin_unlock_irqrestore(&bank->lock, flags);
469 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
471 void __iomem *reg = bank->base;
473 reg += bank->regs->irqstatus;
477 if (bank->regs->irqstatus2) {
478 reg = bank->base + bank->regs->irqstatus2;
486 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
489 omap_clear_gpio_irqbank(bank, BIT(offset));
492 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
494 void __iomem *reg = bank->base;
496 u32 mask = (BIT(bank->width)) - 1;
498 reg += bank->regs->irqenable;
500 if (bank->regs->irqenable_inv)
506 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
509 void __iomem *reg = bank->base;
512 if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {
514 reg += bank->regs->set_irqenable;
515 bank->context.irqenable1 |= gpio_mask;
517 reg += bank->regs->clr_irqenable;
518 bank->context.irqenable1 &= ~gpio_mask;
522 bank->context.irqenable1 =
523 omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,
524 enable ^ bank->regs->irqenable_inv);
533 if (bank->regs->wkup_en &&
534 (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) {
535 bank->context.wake_en =
536 omap_gpio_rmw(bank->base + bank->regs->wkup_en,
544 struct gpio_bank *bank = omap_irq_data_get_bank(d);
546 return irq_set_irq_wake(bank->irq, enable);
550 * We need to unmask the GPIO bank interrupt as soon as possible to
551 * avoid missing GPIO interrupts for other lines in the bank.
553 * in the bank to avoid missing nested interrupts for a GPIO line.
554 * If we wait to unmask individual GPIO lines in the bank after the
563 struct gpio_bank *bank = gpiobank;
567 isr_reg = bank->base + bank->regs->irqstatus;
571 if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
576 raw_spin_lock_irqsave(&bank->lock, lock_flags);
578 enabled = omap_get_gpio_irqbank_mask(bank);
586 edge = isr & ~bank->level_mask;
588 omap_clear_gpio_irqbank(bank, edge);
590 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
599 raw_spin_lock_irqsave(&bank->lock, lock_flags);
605 * This will be indicated in the bank toggle_mask.
607 if (bank->toggle_mask & (BIT(bit)))
608 omap_toggle_gpio_edge_triggering(bank, bit);
610 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
612 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
614 generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
617 raw_spin_unlock_irqrestore(&bank->wa_lock,
627 struct gpio_bank *bank = omap_irq_data_get_bank(d);
631 raw_spin_lock_irqsave(&bank->lock, flags);
633 if (!LINE_USED(bank->mod_usage, offset))
634 omap_set_gpio_direction(bank, offset, 1);
635 omap_enable_gpio_module(bank, offset);
636 bank->irq_usage |= BIT(offset);
638 raw_spin_unlock_irqrestore(&bank->lock, flags);
646 struct gpio_bank *bank = omap_irq_data_get_bank(d);
650 raw_spin_lock_irqsave(&bank->lock, flags);
651 bank->irq_usage &= ~(BIT(offset));
652 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
653 omap_clear_gpio_irqstatus(bank, offset);
654 omap_set_gpio_irqenable(bank, offset, 0);
655 if (!LINE_USED(bank->mod_usage, offset))
656 omap_clear_gpio_debounce(bank, offset);
657 omap_disable_gpio_module(bank, offset);
658 raw_spin_unlock_irqrestore(&bank->lock, flags);
663 struct gpio_bank *bank = omap_irq_data_get_bank(data);
665 pm_runtime_get_sync(bank->chip.parent);
670 struct gpio_bank *bank = omap_irq_data_get_bank(data);
672 pm_runtime_put(bank->chip.parent);
677 struct gpio_bank *bank = omap_irq_data_get_bank(d);
681 raw_spin_lock_irqsave(&bank->lock, flags);
682 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
683 omap_set_gpio_irqenable(bank, offset, 0);
684 raw_spin_unlock_irqrestore(&bank->lock, flags);
689 struct gpio_bank *bank = omap_irq_data_get_bank(d);
694 raw_spin_lock_irqsave(&bank->lock, flags);
695 omap_set_gpio_irqenable(bank, offset, 1);
702 if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
704 omap_clear_gpio_irqstatus(bank, offset);
707 omap_set_gpio_triggering(bank, offset, trigger);
709 raw_spin_unlock_irqrestore(&bank->lock, flags);
716 struct gpio_bank *bank = dev_get_drvdata(dev);
717 void __iomem *mask_reg = bank->base +
718 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
721 raw_spin_lock_irqsave(&bank->lock, flags);
722 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
723 raw_spin_unlock_irqrestore(&bank->lock, flags);
730 struct gpio_bank *bank = dev_get_drvdata(dev);
731 void __iomem *mask_reg = bank->base +
732 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
735 raw_spin_lock_irqsave(&bank->lock, flags);
736 writel_relaxed(bank->context.wake_en, mask_reg);
737 raw_spin_unlock_irqrestore(&bank->lock, flags);
764 static inline void omap_mpuio_init(struct gpio_bank *bank)
766 platform_set_drvdata(&omap_mpuio_device, bank);
776 struct gpio_bank *bank = gpiochip_get_data(chip);
781 raw_spin_lock_irqsave(&bank->lock, flags);
782 omap_enable_gpio_module(bank, offset);
783 bank->mod_usage |= BIT(offset);
784 raw_spin_unlock_irqrestore(&bank->lock, flags);
791 struct gpio_bank *bank = gpiochip_get_data(chip);
794 raw_spin_lock_irqsave(&bank->lock, flags);
795 bank->mod_usage &= ~(BIT(offset));
796 if (!LINE_USED(bank->irq_usage, offset)) {
797 omap_set_gpio_direction(bank, offset, 1);
798 omap_clear_gpio_debounce(bank, offset);
800 omap_disable_gpio_module(bank, offset);
801 raw_spin_unlock_irqrestore(&bank->lock, flags);
808 struct gpio_bank *bank = gpiochip_get_data(chip);
810 if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset))
818 struct gpio_bank *bank;
821 bank = gpiochip_get_data(chip);
822 raw_spin_lock_irqsave(&bank->lock, flags);
823 omap_set_gpio_direction(bank, offset, 1);
824 raw_spin_unlock_irqrestore(&bank->lock, flags);
830 struct gpio_bank *bank = gpiochip_get_data(chip);
833 if (omap_gpio_is_input(bank, offset))
834 reg = bank->base + bank->regs->datain;
836 reg = bank->base + bank->regs->dataout;
843 struct gpio_bank *bank;
846 bank = gpiochip_get_data(chip);
847 raw_spin_lock_irqsave(&bank->lock, flags);
848 bank->set_dataout(bank, offset, value);
849 omap_set_gpio_direction(bank, offset, 0);
850 raw_spin_unlock_irqrestore(&bank->lock, flags);
857 struct gpio_bank *bank = gpiochip_get_data(chip);
858 void __iomem *base = bank->base;
861 direction = readl_relaxed(base + bank->regs->direction);
865 val |= readl_relaxed(base + bank->regs->datain) & m;
869 val |= readl_relaxed(base + bank->regs->dataout) & m;
879 struct gpio_bank *bank;
883 bank = gpiochip_get_data(chip);
885 raw_spin_lock_irqsave(&bank->lock, flags);
886 ret = omap2_set_gpio_debounce(bank, offset, debounce);
887 raw_spin_unlock_irqrestore(&bank->lock, flags);
922 struct gpio_bank *bank;
925 bank = gpiochip_get_data(chip);
926 raw_spin_lock_irqsave(&bank->lock, flags);
927 bank->set_dataout(bank, offset, value);
928 raw_spin_unlock_irqrestore(&bank->lock, flags);
934 struct gpio_bank *bank = gpiochip_get_data(chip);
935 void __iomem *reg = bank->base + bank->regs->dataout;
939 raw_spin_lock_irqsave(&bank->lock, flags);
942 bank->context.dataout = l;
943 raw_spin_unlock_irqrestore(&bank->lock, flags);
948 static void omap_gpio_show_rev(struct gpio_bank *bank)
953 if (called || bank->regs->revision == USHRT_MAX)
956 rev = readw_relaxed(bank->base + bank->regs->revision);
963 static void omap_gpio_mod_init(struct gpio_bank *bank)
965 void __iomem *base = bank->base;
968 if (bank->width == 16)
971 if (bank->is_mpuio) {
972 writel_relaxed(l, bank->base + bank->regs->irqenable);
976 omap_gpio_rmw(base + bank->regs->irqenable, l,
977 bank->regs->irqenable_inv);
978 omap_gpio_rmw(base + bank->regs->irqstatus, l,
979 !bank->regs->irqenable_inv);
980 if (bank->regs->debounce_en)
981 writel_relaxed(0, base + bank->regs->debounce_en);
984 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
986 if (bank->regs->ctrl)
987 writel_relaxed(0, base + bank->regs->ctrl);
990 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1002 bank->chip.request = omap_gpio_request;
1003 bank->chip.free = omap_gpio_free;
1004 bank->chip.get_direction = omap_gpio_get_direction;
1005 bank->chip.direction_input = omap_gpio_input;
1006 bank->chip.get = omap_gpio_get;
1007 bank->chip.get_multiple = omap_gpio_get_multiple;
1008 bank->chip.direction_output = omap_gpio_output;
1009 bank->chip.set_config = omap_gpio_set_config;
1010 bank->chip.set = omap_gpio_set;
1011 bank->chip.set_multiple = omap_gpio_set_multiple;
1012 if (bank->is_mpuio) {
1013 bank->chip.label = "mpuio";
1014 if (bank->regs->wkup_en)
1015 bank->chip.parent = &omap_mpuio_device.dev;
1016 bank->chip.base = OMAP_MPUIO(0);
1018 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1019 gpio, gpio + bank->width - 1);
1022 bank->chip.label = label;
1023 bank->chip.base = gpio;
1025 bank->chip.ngpio = bank->width;
1032 irq_base = devm_irq_alloc_descs(bank->chip.parent,
1033 -1, 0, bank->width, 0);
1035 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1041 if (bank->is_mpuio && !bank->regs->wkup_en)
1044 irq = &bank->chip.irq;
1049 irq->parents = &bank->irq;
1052 ret = gpiochip_add_data(&bank->chip, bank);
1054 dev_err(bank->chip.parent,
1059 ret = devm_request_irq(bank->chip.parent, bank->irq,
1061 0, dev_name(bank->chip.parent), bank);
1063 gpiochip_remove(&bank->chip);
1065 if (!bank->is_mpuio)
1066 gpio += bank->width;
1091 static void omap_gpio_restore_context(struct gpio_bank *bank)
1093 const struct omap_gpio_reg_offs *regs = bank->regs;
1094 void __iomem *base = bank->base;
1096 writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);
1097 writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
1098 writel_relaxed(bank->context.ctrl, base + regs->ctrl);
1099 writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
1100 writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
1101 writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
1102 writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
1103 writel_relaxed(bank->context.dataout, base + regs->dataout);
1104 writel_relaxed(bank->context.oe, base + regs->direction);
1106 if (bank->dbck_enable_mask) {
1107 writel_relaxed(bank->context.debounce, base + regs->debounce);
1108 writel_relaxed(bank->context.debounce_en,
1112 writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
1113 writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
1116 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1118 struct device *dev = bank->chip.parent;
1119 void __iomem *base = bank->base;
1122 bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1125 if (bank->loses_context)
1126 bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig);
1128 if (!bank->enabled_non_wakeup_gpios)
1132 mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect;
1133 mask &= ~bank->context.risingdetect;
1134 bank->saved_datain |= mask;
1137 mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect;
1138 mask &= ~bank->context.fallingdetect;
1139 bank->saved_datain &= ~mask;
1149 if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
1150 nowake = bank->enabled_non_wakeup_gpios;
1151 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
1152 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
1156 if (bank->get_context_loss_count)
1157 bank->context_loss_count =
1158 bank->get_context_loss_count(dev);
1160 omap_gpio_dbck_disable(bank);
1163 static void omap_gpio_unidle(struct gpio_bank *bank)
1165 struct device *dev = bank->chip.parent;
1174 if (bank->loses_context && !bank->context_valid) {
1175 omap_gpio_init_context(bank);
1177 if (bank->get_context_loss_count)
1178 bank->context_loss_count =
1179 bank->get_context_loss_count(dev);
1182 omap_gpio_dbck_enable(bank);
1184 if (bank->loses_context) {
1185 if (!bank->get_context_loss_count) {
1186 omap_gpio_restore_context(bank);
1188 c = bank->get_context_loss_count(dev);
1189 if (c != bank->context_loss_count) {
1190 omap_gpio_restore_context(bank);
1197 writel_relaxed(bank->context.fallingdetect,
1198 bank->base + bank->regs->fallingdetect);
1199 writel_relaxed(bank->context.risingdetect,
1200 bank->base + bank->regs->risingdetect);
1203 l = readl_relaxed(bank->base + bank->regs->datain);
1211 l ^= bank->saved_datain;
1212 l &= bank->enabled_non_wakeup_gpios;
1218 gen0 = l & bank->context.fallingdetect;
1219 gen0 &= bank->saved_datain;
1221 gen1 = l & bank->context.risingdetect;
1222 gen1 &= ~(bank->saved_datain);
1225 gen = l & (~(bank->context.fallingdetect) &
1226 ~(bank->context.risingdetect));
1233 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1234 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1236 if (!bank->regs->irqstatus_raw0) {
1237 writel_relaxed(old0 | gen, bank->base +
1238 bank->regs->leveldetect0);
1239 writel_relaxed(old1 | gen, bank->base +
1240 bank->regs->leveldetect1);
1243 if (bank->regs->irqstatus_raw0) {
1244 writel_relaxed(old0 | l, bank->base +
1245 bank->regs->leveldetect0);
1246 writel_relaxed(old1 | l, bank->base +
1247 bank->regs->leveldetect1);
1249 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1250 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1257 struct gpio_bank *bank;
1262 bank = container_of(nb, struct gpio_bank, nb);
1264 raw_spin_lock_irqsave(&bank->lock, flags);
1265 if (bank->is_suspended)
1270 mask = omap_get_gpio_irqbank_mask(bank);
1271 isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask;
1276 omap_gpio_idle(bank, true);
1280 omap_gpio_unidle(bank);
1285 raw_spin_unlock_irqrestore(&bank->lock, flags);
1381 struct gpio_bank *bank;
1391 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1392 if (!bank)
1412 bank->irq = platform_get_irq(pdev, 0);
1413 if (bank->irq <= 0) {
1414 if (!bank->irq)
1415 bank->irq = -ENXIO;
1416 return dev_err_probe(dev, bank->irq, "can't get irq resource\n");
1419 bank->chip.parent = dev;
1420 bank->chip.owner = THIS_MODULE;
1421 bank->dbck_flag = pdata->dbck_flag;
1422 bank->stride = pdata->bank_stride;
1423 bank->width = pdata->bank_width;
1424 bank->is_mpuio = pdata->is_mpuio;
1425 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1426 bank->regs = pdata->regs;
1428 bank->chip.of_node = of_node_get(node);
1433 bank->loses_context = true;
1435 bank->loses_context = pdata->loses_context;
1437 if (bank->loses_context)
1438 bank->get_context_loss_count =
1442 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1443 bank->set_dataout = omap_set_gpio_dataout_reg;
1445 bank->set_dataout = omap_set_gpio_dataout_mask;
1447 raw_spin_lock_init(&bank->lock);
1448 raw_spin_lock_init(&bank->wa_lock);
1451 bank->base = devm_platform_ioremap_resource(pdev, 0);
1452 if (IS_ERR(bank->base)) {
1453 return PTR_ERR(bank->base);
1456 if (bank->dbck_flag) {
1457 bank->dbck = devm_clk_get(dev, "dbclk");
1458 if (IS_ERR(bank->dbck)) {
1461 bank->dbck_flag = false;
1463 clk_prepare(bank->dbck);
1467 platform_set_drvdata(pdev, bank);
1472 if (bank->is_mpuio)
1473 omap_mpuio_init(bank);
1475 omap_gpio_mod_init(bank);
1477 ret = omap_gpio_chip_init(bank, irqc);
1481 if (bank->dbck_flag)
1482 clk_unprepare(bank->dbck);
1486 omap_gpio_show_rev(bank);
1488 bank->nb.notifier_call = gpio_omap_cpu_notifier;
1489 cpu_pm_register_notifier(&bank->nb);
1498 struct gpio_bank *bank = platform_get_drvdata(pdev);
1500 cpu_pm_unregister_notifier(&bank->nb);
1501 gpiochip_remove(&bank->chip);
1503 if (bank->dbck_flag)
1504 clk_unprepare(bank->dbck);
1511 struct gpio_bank *bank = dev_get_drvdata(dev);
1514 raw_spin_lock_irqsave(&bank->lock, flags);
1515 omap_gpio_idle(bank, true);
1516 bank->is_suspended = true;
1517 raw_spin_unlock_irqrestore(&bank->lock, flags);
1524 struct gpio_bank *bank = dev_get_drvdata(dev);
1527 raw_spin_lock_irqsave(&bank->lock, flags);
1528 omap_gpio_unidle(bank);
1529 bank->is_suspended = false;
1530 raw_spin_unlock_irqrestore(&bank->lock, flags);
1537 struct gpio_bank *bank = dev_get_drvdata(dev);
1539 if (bank->is_suspended)
1542 bank->needs_resume = 1;
1549 struct gpio_bank *bank = dev_get_drvdata(dev);
1551 if (!bank->needs_resume)
1554 bank->needs_resume = 0;