Lines Matching refs:port
58 static inline int is_imx23_gpio(struct mxs_gpio_port *port)
60 return port->devid == IMX23_GPIO;
63 static inline int is_imx28_gpio(struct mxs_gpio_port *port)
65 return port->devid == IMX28_GPIO;
76 struct mxs_gpio_port *port = gc->private;
84 port->both_edges &= ~pin_mask;
87 val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
92 port->both_edges |= pin_mask;
111 pin_addr = port->base + PINCTRL_IRQLEV(port);
114 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
117 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
121 pin_addr = port->base + PINCTRL_IRQPOL(port);
127 writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
132 static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
139 pin_addr = port->base + PINCTRL_IRQPOL(port);
149 /* MXS has one interrupt *per* gpio port */
153 struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
157 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
158 readl(port->base + PINCTRL_IRQEN(port));
162 if (port->both_edges & (1 << irqoffset))
163 mxs_flip_edge(port, irqoffset);
165 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
182 struct mxs_gpio_port *port = gc->private;
185 enable_irq_wake(port->irq);
187 disable_irq_wake(port->irq);
192 static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
198 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
199 port->base, handle_level_irq);
203 gc->private = port;
213 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
214 ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
215 ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
225 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
226 ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
227 ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
230 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
239 struct mxs_gpio_port *port = gpiochip_get_data(gc);
241 return irq_find_mapping(port->domain, offset);
246 struct mxs_gpio_port *port = gpiochip_get_data(gc);
250 dir = readl(port->base + PINCTRL_DOE(port));
282 struct mxs_gpio_port *port;
286 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
287 if (!port)
290 port->id = of_alias_get_id(np, "gpio");
291 if (port->id < 0)
292 return port->id;
293 port->devid = (enum mxs_gpio_id)of_device_get_match_data(&pdev->dev);
294 port->dev = &pdev->dev;
295 port->irq = platform_get_irq(pdev, 0);
296 if (port->irq < 0)
297 return port->irq;
310 port->base = base;
313 writel(0, port->base + PINCTRL_PIN2IRQ(port));
314 writel(0, port->base + PINCTRL_IRQEN(port));
317 writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
325 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
327 if (!port->domain) {
333 err = mxs_gpio_init_gc(port, irq_base);
338 irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
339 port);
341 err = bgpio_init(&port->gc, &pdev->dev, 4,
342 port->base + PINCTRL_DIN(port),
343 port->base + PINCTRL_DOUT(port) + MXS_SET,
344 port->base + PINCTRL_DOUT(port) + MXS_CLR,
345 port->base + PINCTRL_DOE(port), NULL, 0);
349 port->gc.to_irq = mxs_gpio_to_irq;
350 port->gc.get_direction = mxs_gpio_get_direction;
351 port->gc.base = port->id * 32;
353 err = gpiochip_add_data(&port->gc, port);
360 irq_domain_remove(port->domain);
362 iounmap(port->base);