Lines Matching refs:port
176 struct mxc_gpio_port *port = gc->private;
180 void __iomem *reg = port->base;
182 port->both_edges &= ~(1 << gpio_idx);
194 val = port->gc.get(&port->gc, gpio_idx);
202 port->both_edges |= 1 << gpio_idx;
216 val = readl(port->base + GPIO_EDGE_SEL);
219 port->base + GPIO_EDGE_SEL);
222 port->base + GPIO_EDGE_SEL);
232 writel(1 << gpio_idx, port->base + GPIO_ISR);
234 return port->gc.direction_input(&port->gc, gpio_idx);
237 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
239 void __iomem *reg = port->base;
263 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
268 if (port->both_edges & (1 << irqoffset))
269 mxc_flip_edge(port, irqoffset);
271 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
277 /* MX1 and MX3 has one interrupt *per* gpio port */
281 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
286 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
288 mxc_gpio_irq_handler(port, irq_stat);
297 struct mxc_gpio_port *port;
303 list_for_each_entry(port, &mxc_gpio_ports, node) {
304 irq_msk = readl(port->base + GPIO_IMR);
308 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
310 mxc_gpio_irq_handler(port, irq_stat);
327 struct mxc_gpio_port *port = gc->private;
332 if (port->irq_high && (gpio_idx >= 16))
333 ret = enable_irq_wake(port->irq_high);
335 ret = enable_irq_wake(port->irq);
337 if (port->irq_high && (gpio_idx >= 16))
338 ret = disable_irq_wake(port->irq_high);
340 ret = disable_irq_wake(port->irq);
346 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
352 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
353 port->base, handle_level_irq);
356 gc->private = port;
368 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
407 struct mxc_gpio_port *port = gpiochip_get_data(gc);
409 return irq_find_mapping(port->domain, offset);
415 struct mxc_gpio_port *port;
422 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
423 if (!port)
426 port->dev = &pdev->dev;
428 port->base = devm_platform_ioremap_resource(pdev, 0);
429 if (IS_ERR(port->base))
430 return PTR_ERR(port->base);
437 port->irq_high = platform_get_irq(pdev, 1);
438 if (port->irq_high < 0)
439 port->irq_high = 0;
442 port->irq = platform_get_irq(pdev, 0);
443 if (port->irq < 0)
444 return port->irq;
447 port->clk = devm_clk_get_optional(&pdev->dev, NULL);
448 if (IS_ERR(port->clk))
449 return PTR_ERR(port->clk);
451 err = clk_prepare_enable(port->clk);
458 port->power_off = true;
461 writel(0, port->base + GPIO_IMR);
462 writel(~0, port->base + GPIO_ISR);
467 * the handler is needed only once, but doing it for every port
470 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
473 irq_set_chained_handler_and_data(port->irq,
474 mx3_gpio_irq_handler, port);
475 if (port->irq_high > 0)
477 irq_set_chained_handler_and_data(port->irq_high,
479 port);
482 err = bgpio_init(&port->gc, &pdev->dev, 4,
483 port->base + GPIO_PSR,
484 port->base + GPIO_DR, NULL,
485 port->base + GPIO_GDIR, NULL,
490 port->gc.request = gpiochip_generic_request;
491 port->gc.free = gpiochip_generic_free;
492 port->gc.to_irq = mxc_gpio_to_irq;
493 port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
496 err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
506 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
508 if (!port->domain) {
514 err = mxc_gpio_init_gc(port, irq_base);
518 list_add_tail(&port->node, &mxc_gpio_ports);
520 platform_set_drvdata(pdev, port);
525 irq_domain_remove(port->domain);
527 clk_disable_unprepare(port->clk);
532 static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
534 if (!port->power_off)
537 port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
538 port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
539 port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
540 port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
541 port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
542 port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
545 static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
547 if (!port->power_off)
550 writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
551 writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
552 writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
553 writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
554 writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
555 writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
560 struct mxc_gpio_port *port;
563 list_for_each_entry(port, &mxc_gpio_ports, node) {
564 mxc_gpio_save_regs(port);
565 clk_disable_unprepare(port->clk);
573 struct mxc_gpio_port *port;
577 list_for_each_entry(port, &mxc_gpio_ports, node) {
578 ret = clk_prepare_enable(port->clk);
583 mxc_gpio_restore_regs(port);