Lines Matching refs:mvchip
101 struct mvebu_gpio_chip *mvchip;
136 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
141 switch (mvchip->soc_variant) {
145 *map = mvchip->regs;
146 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
150 *map = mvchip->percpu_regs;
159 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
165 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
172 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
177 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
182 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
187 switch (mvchip->soc_variant) {
190 *map = mvchip->regs;
191 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
195 *map = mvchip->regs;
200 *map = mvchip->percpu_regs;
209 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
215 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
222 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
227 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
232 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
237 switch (mvchip->soc_variant) {
240 *map = mvchip->regs;
241 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
245 *map = mvchip->regs;
250 *map = mvchip->percpu_regs;
259 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
265 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
272 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
277 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
300 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
302 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
308 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
311 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
316 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
318 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
322 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
331 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
333 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
339 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
350 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
359 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
373 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
381 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
384 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
394 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
396 return irq_create_mapping(mvchip->domain, pin);
405 struct mvebu_gpio_chip *mvchip = gc->private;
409 mvebu_gpio_write_edge_cause(mvchip, ~mask);
416 struct mvebu_gpio_chip *mvchip = gc->private;
422 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
429 struct mvebu_gpio_chip *mvchip = gc->private;
434 mvebu_gpio_write_edge_cause(mvchip, ~mask);
436 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
443 struct mvebu_gpio_chip *mvchip = gc->private;
449 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
456 struct mvebu_gpio_chip *mvchip = gc->private;
462 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
496 struct mvebu_gpio_chip *mvchip = gc->private;
502 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
521 regmap_update_bits(mvchip->regs,
522 GPIO_IN_POL_OFF + mvchip->offset,
527 regmap_update_bits(mvchip->regs,
528 GPIO_IN_POL_OFF + mvchip->offset,
534 regmap_read(mvchip->regs,
535 GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
536 regmap_read(mvchip->regs,
537 GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
547 regmap_update_bits(mvchip->regs,
548 GPIO_IN_POL_OFF + mvchip->offset,
558 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
563 if (mvchip == NULL)
568 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
569 level_mask = mvebu_gpio_read_level_mask(mvchip);
570 edge_cause = mvebu_gpio_read_edge_cause(mvchip);
571 edge_mask = mvebu_gpio_read_edge_mask(mvchip);
575 for (i = 0; i < mvchip->chip.ngpio; i++) {
578 irq = irq_find_mapping(mvchip->domain, i);
588 regmap_read(mvchip->regs,
589 GPIO_IN_POL_OFF + mvchip->offset,
592 regmap_write(mvchip->regs,
593 GPIO_IN_POL_OFF + mvchip->offset,
614 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
624 desc = gpiochip_request_own_desc(&mvchip->chip,
656 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
685 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
698 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
730 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
732 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
747 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
749 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
751 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
759 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
761 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
763 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
772 struct mvebu_gpio_chip *mvchip,
779 if (!of_device_is_compatible(mvchip->chip.of_node,
792 if (IS_ERR(mvchip->clk))
793 return PTR_ERR(mvchip->clk);
805 regmap_write(mvchip->regs,
806 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
811 mvchip->mvpwm = mvpwm;
812 mvpwm->mvchip = mvchip;
818 mvpwm->clk_rate = clk_get_rate(mvchip->clk);
826 mvpwm->chip.npwm = mvchip->chip.ngpio;
829 * mvpwm->chip.base to a fixed point like mvchip->chip.base.
845 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
850 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
851 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
852 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
853 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
854 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
855 cause = mvebu_gpio_read_edge_cause(mvchip);
856 edg_msk = mvebu_gpio_read_edge_mask(mvchip);
857 lvl_msk = mvebu_gpio_read_level_mask(mvchip);
921 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
924 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
925 &mvchip->out_reg);
926 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
927 &mvchip->io_conf_reg);
928 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
929 &mvchip->blink_en_reg);
930 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
931 &mvchip->in_pol_reg);
933 switch (mvchip->soc_variant) {
936 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
937 &mvchip->edge_mask_regs[0]);
938 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
939 &mvchip->level_mask_regs[0]);
943 regmap_read(mvchip->regs,
945 &mvchip->edge_mask_regs[i]);
946 regmap_read(mvchip->regs,
948 &mvchip->level_mask_regs[i]);
953 regmap_read(mvchip->regs,
955 &mvchip->edge_mask_regs[i]);
956 regmap_read(mvchip->regs,
958 &mvchip->level_mask_regs[i]);
966 mvebu_pwm_suspend(mvchip);
973 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
976 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
977 mvchip->out_reg);
978 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
979 mvchip->io_conf_reg);
980 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
981 mvchip->blink_en_reg);
982 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
983 mvchip->in_pol_reg);
985 switch (mvchip->soc_variant) {
988 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
989 mvchip->edge_mask_regs[0]);
990 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
991 mvchip->level_mask_regs[0]);
995 regmap_write(mvchip->regs,
997 mvchip->edge_mask_regs[i]);
998 regmap_write(mvchip->regs,
1000 mvchip->level_mask_regs[i]);
1005 regmap_write(mvchip->regs,
1007 mvchip->edge_mask_regs[i]);
1008 regmap_write(mvchip->regs,
1010 mvchip->level_mask_regs[i]);
1018 mvebu_pwm_resume(mvchip);
1031 struct mvebu_gpio_chip *mvchip)
1039 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1041 if (IS_ERR(mvchip->regs))
1042 return PTR_ERR(mvchip->regs);
1048 mvchip->offset = 0;
1054 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1059 mvchip->percpu_regs =
1062 if (IS_ERR(mvchip->percpu_regs))
1063 return PTR_ERR(mvchip->percpu_regs);
1070 struct mvebu_gpio_chip *mvchip)
1072 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1073 if (IS_ERR(mvchip->regs))
1074 return PTR_ERR(mvchip->regs);
1076 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
1084 struct mvebu_gpio_chip *mvchip;
1108 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1110 if (!mvchip)
1113 platform_set_drvdata(pdev, mvchip);
1126 mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1128 if (!IS_ERR(mvchip->clk))
1129 clk_prepare_enable(mvchip->clk);
1131 mvchip->soc_variant = soc_variant;
1132 mvchip->chip.label = dev_name(&pdev->dev);
1133 mvchip->chip.parent = &pdev->dev;
1134 mvchip->chip.request = gpiochip_generic_request;
1135 mvchip->chip.free = gpiochip_generic_free;
1136 mvchip->chip.get_direction = mvebu_gpio_get_direction;
1137 mvchip->chip.direction_input = mvebu_gpio_direction_input;
1138 mvchip->chip.get = mvebu_gpio_get;
1139 mvchip->chip.direction_output = mvebu_gpio_direction_output;
1140 mvchip->chip.set = mvebu_gpio_set;
1142 mvchip->chip.to_irq = mvebu_gpio_to_irq;
1143 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1144 mvchip->chip.ngpio = ngpios;
1145 mvchip->chip.can_sleep = false;
1146 mvchip->chip.of_node = np;
1147 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1150 err = mvebu_gpio_probe_syscon(pdev, mvchip);
1152 err = mvebu_gpio_probe_raw(pdev, mvchip);
1163 regmap_write(mvchip->regs,
1164 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1165 regmap_write(mvchip->regs,
1166 GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1167 regmap_write(mvchip->regs,
1168 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1171 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1173 regmap_write(mvchip->regs,
1175 regmap_write(mvchip->regs,
1180 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1181 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1182 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1184 regmap_write(mvchip->percpu_regs,
1186 regmap_write(mvchip->percpu_regs,
1188 regmap_write(mvchip->percpu_regs,
1196 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1200 err = mvebu_pwm_probe(pdev, mvchip, id);
1209 mvchip->domain =
1211 if (!mvchip->domain) {
1213 mvchip->chip.label);
1219 mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1223 mvchip->chip.label);
1231 gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1232 gc->private = mvchip;
1238 ct->chip.name = mvchip->chip.label;
1247 ct->chip.name = mvchip->chip.label;
1260 mvchip);
1266 irq_domain_remove(mvchip->domain);
1268 pwmchip_remove(&mvchip->mvpwm->chip);