Lines Matching defs:rg
67 mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
69 struct gpio_chip *gc = &rg->chip;
72 offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
77 mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
79 struct gpio_chip *gc = &rg->chip;
82 offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
90 struct mtk_gc *rg = to_mediatek_gpio(gc);
95 pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
101 mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
112 struct mtk_gc *rg = to_mediatek_gpio(gc);
117 spin_lock_irqsave(&rg->lock, flags);
118 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
119 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
120 high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
121 low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
122 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising));
123 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling));
124 mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel));
125 mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel));
126 spin_unlock_irqrestore(&rg->lock, flags);
133 struct mtk_gc *rg = to_mediatek_gpio(gc);
138 spin_lock_irqsave(&rg->lock, flags);
139 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
140 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
141 high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
142 low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
143 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
144 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
145 mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
146 mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
147 spin_unlock_irqrestore(&rg->lock, flags);
154 struct mtk_gc *rg = to_mediatek_gpio(gc);
159 if ((rg->rising | rg->falling |
160 rg->hlevel | rg->llevel) & mask)
166 rg->rising &= ~mask;
167 rg->falling &= ~mask;
168 rg->hlevel &= ~mask;
169 rg->llevel &= ~mask;
173 rg->rising |= mask;
174 rg->falling |= mask;
177 rg->rising |= mask;
180 rg->falling |= mask;
183 rg->hlevel |= mask;
186 rg->llevel |= mask;
198 struct mtk_gc *rg = to_mediatek_gpio(chip);
200 if (rg->bank != gpio / MTK_BANK_WIDTH)
214 struct mtk_gc *rg;
218 rg = &mtk->gc_map[bank];
219 memset(rg, 0, sizeof(*rg));
221 spin_lock_init(&rg->lock);
222 rg->chip.of_node = node;
223 rg->bank = bank;
225 dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
226 set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);
227 ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);
228 diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);
230 ret = bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL,
237 rg->chip.of_gpio_n_cells = 2;
238 rg->chip.of_xlate = mediatek_gpio_xlate;
239 rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d",
241 if (!rg->chip.label)
244 rg->irq_chip.name = dev_name(dev);
245 rg->irq_chip.parent_device = dev;
246 rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask;
247 rg->irq_chip.irq_mask = mediatek_gpio_irq_mask;
248 rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask;
249 rg->irq_chip.irq_set_type = mediatek_gpio_irq_type;
260 rg->chip.label, &rg->chip);
268 girq = &rg->chip.irq;
269 girq->chip = &rg->irq_chip;
278 ret = devm_gpiochip_add_data(dev, &rg->chip, mtk);
281 rg->chip.ngpio, ret);
286 mtk_gpio_w32(rg, GPIO_REG_POL, 0);
288 dev_info(dev, "registering %d gpios\n", rg->chip.ngpio);