Lines Matching refs:set
23 * . register the device with -be`. .with a pair of set/clear-bit registers ,
341 gc->set(gc, gpio, val);
406 gc->set(gc, gpio, val);
413 gc->set(gc, gpio, val);
471 * - set/clear pair (named "set" and "clr").
472 * - single output register resource and single input resource ("set" and
476 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
477 * in the set register and clears it by setting a bit in the clear register.
490 void __iomem *set,
499 if (set && clr) {
500 gc->reg_set = set;
502 gc->set = bgpio_set_with_clear;
504 } else if (set && !clr) {
505 gc->reg_set = set;
506 gc->set = bgpio_set_set;
509 gc->set = bgpio_set_none;
512 gc->set = bgpio_set;
524 * their value in the set register when used as output. It is
574 * @gc: the GPIO chip to set up
580 * @set: MMIO address for the register to SET the value of the GPIO lines, it is
588 * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
592 * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
600 unsigned long sz, void __iomem *dat, void __iomem *set,
621 ret = bgpio_setup_io(gc, dat, set, clr, flags);
634 if (gc->set == bgpio_set_set &&
729 void __iomem *set;
758 set = bgpio_map(pdev, "set", sz);
759 if (IS_ERR(set))
760 return PTR_ERR(set);
778 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);