Lines Matching defs:hlwd
60 struct hlwd_gpio *hlwd =
68 spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
69 pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
70 pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
73 emulated_pending = hlwd->edge_emulation & pending;
78 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
84 hlwd->regs + HW_GPIOB_INTLVL);
87 iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
90 rising &= hlwd->rising_edge;
91 falling &= hlwd->falling_edge;
96 spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
101 int irq = irq_find_mapping(hlwd->gpioc.irq.domain, hwirq);
111 struct hlwd_gpio *hlwd =
114 iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
119 struct hlwd_gpio *hlwd =
124 spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
125 mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
127 iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
128 spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
133 struct hlwd_gpio *hlwd =
138 spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
139 mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
141 iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
142 spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
151 static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,
157 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
158 state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);
161 iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
163 hlwd->edge_emulation |= BIT(hwirq);
164 hlwd->rising_edge &= ~BIT(hwirq);
165 hlwd->falling_edge &= ~BIT(hwirq);
167 hlwd->rising_edge |= BIT(hwirq);
169 hlwd->falling_edge |= BIT(hwirq);
174 struct hlwd_gpio *hlwd =
179 spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
181 hlwd->edge_emulation &= ~BIT(data->hwirq);
185 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
187 iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
190 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
192 iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
197 hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
200 spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
204 spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
210 struct hlwd_gpio *hlwd;
214 hlwd = devm_kzalloc(&pdev->dev, sizeof(*hlwd), GFP_KERNEL);
215 if (!hlwd)
218 hlwd->regs = devm_platform_ioremap_resource(pdev, 0);
219 if (IS_ERR(hlwd->regs))
220 return PTR_ERR(hlwd->regs);
231 iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);
233 res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4,
234 hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT,
235 NULL, hlwd->regs + HW_GPIOB_DIR, NULL,
245 hlwd->gpioc.ngpio = ngpios;
248 iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
249 iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);
258 hlwd->irq = platform_get_irq(pdev, 0);
259 if (hlwd->irq < 0) {
261 hlwd->irq);
262 return hlwd->irq;
265 hlwd->irqc.name = dev_name(&pdev->dev);
266 hlwd->irqc.irq_mask = hlwd_gpio_irq_mask;
267 hlwd->irqc.irq_unmask = hlwd_gpio_irq_unmask;
268 hlwd->irqc.irq_enable = hlwd_gpio_irq_enable;
269 hlwd->irqc.irq_set_type = hlwd_gpio_irq_set_type;
271 girq = &hlwd->gpioc.irq;
272 girq->chip = &hlwd->irqc;
280 girq->parents[0] = hlwd->irq;
285 return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
296 .name = "gpio-hlwd",