Lines Matching refs:epg
80 static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg,
83 writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
86 epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);
89 epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);
92 epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
98 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
108 epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);
114 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
127 stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
129 generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain,
132 stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
134 generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain,
161 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
166 ep93xx_gpio_update_int_params(epg, eic);
169 writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
176 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
183 ep93xx_gpio_update_int_params(epg, eic);
185 writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
192 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
195 ep93xx_gpio_update_int_params(epg, eic);
202 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
205 ep93xx_gpio_update_int_params(epg, eic);
217 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
262 ep93xx_gpio_update_int_params(epg, eic);
337 struct ep93xx_gpio *epg,
340 void __iomem *data = epg->base + bank->data;
341 void __iomem *dir = epg->base + bank->dir;
410 irq_set_chip_data(gpio_irq, &epg->gc[5]);
421 return devm_gpiochip_add_data(dev, gc, epg);
426 struct ep93xx_gpio *epg;
429 epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
430 if (!epg)
433 epg->base = devm_platform_ioremap_resource(pdev, 0);
434 if (IS_ERR(epg->base))
435 return PTR_ERR(epg->base);
438 struct ep93xx_gpio_chip *gc = &epg->gc[i];
441 if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))