Lines Matching refs:offset
140 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
145 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
153 tmp |= BIT(SPRD_EIC_BIT(offset));
155 tmp &= ~BIT(SPRD_EIC_BIT(offset));
161 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
165 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
167 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
170 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
172 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);
176 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
178 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);
181 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
187 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
189 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA);
191 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA);
197 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
203 static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
208 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
213 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
214 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
223 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
230 return sprd_eic_set_debounce(chip, offset, arg);
239 u32 offset = irqd_to_hwirq(data);
243 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);
244 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);
247 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);
250 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);
253 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);
264 u32 offset = irqd_to_hwirq(data);
268 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);
269 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);
272 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);
275 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);
278 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);
289 u32 offset = irqd_to_hwirq(data);
293 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
296 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
299 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
302 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
313 u32 offset = irqd_to_hwirq(data);
320 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
321 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
324 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
325 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
330 state = sprd_eic_get(chip, offset);
332 sprd_eic_update(chip, offset,
334 sprd_eic_update(chip, offset,
337 sprd_eic_update(chip, offset,
339 sprd_eic_update(chip, offset,
352 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
353 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
356 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
357 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
362 state = sprd_eic_get(chip, offset);
364 sprd_eic_update(chip, offset,
366 sprd_eic_update(chip, offset,
369 sprd_eic_update(chip, offset,
371 sprd_eic_update(chip, offset,
384 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
385 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
386 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
387 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
391 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
392 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
393 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
394 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
398 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
399 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
400 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
404 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
405 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
406 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
407 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
411 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
412 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
413 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
414 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
424 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
425 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
426 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
427 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
431 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
432 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
433 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
434 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
438 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
439 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
440 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
444 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
445 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
446 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
447 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
451 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
452 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
453 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
454 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
470 unsigned int offset)
487 state = sprd_eic_get(chip, offset);
493 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
495 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
499 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
501 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
508 post_state = sprd_eic_get(chip, offset);
557 u32 offset = bank * SPRD_EIC_PER_BANK_NR + n;
559 girq = irq_find_mapping(chip->irq.domain, offset);
562 sprd_eic_toggle_trigger(chip, girq, offset);