Lines Matching refs:gpio
10 #include <linux/gpio/driver.h>
25 #include <linux/platform_data/gpio-dwapb.h>
51 #define DWAPB_DRIVER_NAME "gpio-dwapb"
94 struct dwapb_gpio *gpio;
101 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
131 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
133 if (gpio->flags & GPIO_REG_OFFSET_V2)
139 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
141 struct gpio_chip *gc = &gpio->ports[0].gc;
142 void __iomem *reg_base = gpio->regs;
144 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
147 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
150 struct gpio_chip *gc = &gpio->ports[0].gc;
151 void __iomem *reg_base = gpio->regs;
153 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
156 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
161 for (i = 0; i < gpio->nr_ports; i++) {
162 port = &gpio->ports[i];
170 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
172 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
181 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
189 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
192 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
194 struct gpio_chip *gc = &gpio->ports[0].gc;
198 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
206 dwapb_toggle_trigger(gpio, hwirq);
214 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
218 dwapb_do_irq(gpio);
230 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
235 dwapb_write(gpio, GPIO_PORTA_EOI, val);
242 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
247 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d));
248 dwapb_write(gpio, GPIO_INTMASK, val);
255 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
260 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d));
261 dwapb_write(gpio, GPIO_INTMASK, val);
268 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
273 val = dwapb_read(gpio, GPIO_INTEN);
275 dwapb_write(gpio, GPIO_INTEN, val);
282 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
287 val = dwapb_read(gpio, GPIO_INTEN);
289 dwapb_write(gpio, GPIO_INTEN, val);
296 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
304 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
305 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
310 dwapb_toggle_trigger(gpio, bit);
335 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
337 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
347 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
348 struct dwapb_context *ctx = gpio->ports[0].ctx;
364 struct dwapb_gpio *gpio = port->gpio;
370 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
375 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
410 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
419 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
424 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
447 girq->parent_handler_data = gpio;
459 err = devm_request_irq(gpio->dev, pp->irq[0],
461 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
463 dev_err(gpio->dev, "error requesting IRQ\n");
473 devm_kfree(gpio->dev, pirq);
476 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
484 port = &gpio->ports[offs];
485 port->gpio = gpio;
489 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
494 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
495 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
496 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
499 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
502 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
519 dwapb_configure_irqs(gpio, port, pp);
521 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
523 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
609 struct dwapb_gpio *gpio = data;
611 reset_control_assert(gpio->rst);
614 static int dwapb_get_reset(struct dwapb_gpio *gpio)
618 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
619 if (IS_ERR(gpio->rst)) {
620 dev_err(gpio->dev, "Cannot get reset descriptor\n");
621 return PTR_ERR(gpio->rst);
624 err = reset_control_deassert(gpio->rst);
626 dev_err(gpio->dev, "Cannot deassert reset lane\n");
630 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
635 struct dwapb_gpio *gpio = data;
637 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
640 static int dwapb_get_clks(struct dwapb_gpio *gpio)
645 gpio->clks[0].id = "bus";
646 gpio->clks[1].id = "db";
647 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
648 gpio->clks);
650 return dev_err_probe(gpio->dev, err,
653 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
655 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
659 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
663 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
664 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
680 struct dwapb_gpio *gpio;
694 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
695 if (!gpio)
698 gpio->dev = &pdev->dev;
699 gpio->nr_ports = pdata->nports;
701 err = dwapb_get_reset(gpio);
705 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
706 sizeof(*gpio->ports), GFP_KERNEL);
707 if (!gpio->ports)
710 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
711 if (IS_ERR(gpio->regs))
712 return PTR_ERR(gpio->regs);
714 err = dwapb_get_clks(gpio);
718 gpio->flags = (uintptr_t)device_get_match_data(dev);
720 for (i = 0; i < gpio->nr_ports; i++) {
721 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
726 platform_set_drvdata(pdev, gpio);
734 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
735 struct gpio_chip *gc = &gpio->ports[0].gc;
740 for (i = 0; i < gpio->nr_ports; i++) {
742 unsigned int idx = gpio->ports[i].idx;
743 struct dwapb_context *ctx = gpio->ports[i].ctx;
746 ctx->dir = dwapb_read(gpio, offset);
749 ctx->data = dwapb_read(gpio, offset);
752 ctx->ext = dwapb_read(gpio, offset);
756 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
757 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
758 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
759 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
760 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
763 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
768 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
775 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
776 struct gpio_chip *gc = &gpio->ports[0].gc;
780 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
782 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
787 for (i = 0; i < gpio->nr_ports; i++) {
789 unsigned int idx = gpio->ports[i].idx;
790 struct dwapb_context *ctx = gpio->ports[i].ctx;
793 dwapb_write(gpio, offset, ctx->data);
796 dwapb_write(gpio, offset, ctx->dir);
799 dwapb_write(gpio, offset, ctx->ext);
803 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
804 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
805 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
806 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
807 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
810 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);