Lines Matching defs:gpio
11 #include <linux/gpio/driver.h>
81 static inline int to_reg(int gpio, enum ctrl_register reg_type)
85 if (gpio >= CRYSTALCOVE_GPIO_NUM) {
90 switch (gpio) {
99 if (gpio < 8)
104 if (gpio < 8)
110 return reg + gpio % 8;
114 int gpio)
116 u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
117 int mask = BIT(gpio % 8);
125 static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
127 int reg = to_reg(gpio, CTRL_IN);
132 static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
135 int reg = to_reg(gpio, CTRL_OUT);
143 static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
147 int reg = to_reg(gpio, CTRL_OUT);
155 static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
159 int ret, reg = to_reg(gpio, CTRL_IN);
172 unsigned int gpio, int value)
175 int reg = to_reg(gpio, CTRL_OUT);
228 int gpio = data->hwirq;
231 crystalcove_update_irq_ctrl(cg, gpio);
233 crystalcove_update_irq_mask(cg, gpio);
276 int gpio;
288 for_each_set_bit(gpio, &pending, CRYSTALCOVE_GPIO_NUM) {
289 virq = irq_find_mapping(cg->chip.irq.domain, gpio);
300 int gpio, offset;
303 for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
304 regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
305 regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
306 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
308 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
310 regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
313 offset = gpio % 8;
314 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
315 gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
377 dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);