Lines Matching defs:cg
113 static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
119 if (cg->set_irq_mask)
120 regmap_update_bits(cg->regmap, mirqs0, mask, mask);
122 regmap_update_bits(cg->regmap, mirqs0, mask, 0);
125 static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
129 regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
134 struct crystalcove_gpio *cg = gpiochip_get_data(chip);
140 return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
146 struct crystalcove_gpio *cg = gpiochip_get_data(chip);
152 return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
157 struct crystalcove_gpio *cg = gpiochip_get_data(chip);
164 ret = regmap_read(cg->regmap, reg, &val);
174 struct crystalcove_gpio *cg = gpiochip_get_data(chip);
181 regmap_update_bits(cg->regmap, reg, 1, 1);
183 regmap_update_bits(cg->regmap, reg, 1, 0);
188 struct crystalcove_gpio *cg =
196 cg->intcnt_value = CTLI_INTCNT_DIS;
199 cg->intcnt_value = CTLI_INTCNT_BE;
202 cg->intcnt_value = CTLI_INTCNT_PE;
205 cg->intcnt_value = CTLI_INTCNT_NE;
211 cg->update |= UPDATE_IRQ_TYPE;
218 struct crystalcove_gpio *cg =
221 mutex_lock(&cg->buslock);
226 struct crystalcove_gpio *cg =
230 if (cg->update & UPDATE_IRQ_TYPE)
231 crystalcove_update_irq_ctrl(cg, gpio);
232 if (cg->update & UPDATE_IRQ_MASK)
233 crystalcove_update_irq_mask(cg, gpio);
234 cg->update = 0;
236 mutex_unlock(&cg->buslock);
241 struct crystalcove_gpio *cg =
245 cg->set_irq_mask = false;
246 cg->update |= UPDATE_IRQ_MASK;
252 struct crystalcove_gpio *cg =
256 cg->set_irq_mask = true;
257 cg->update |= UPDATE_IRQ_MASK;
273 struct crystalcove_gpio *cg = data;
279 if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
280 regmap_read(cg->regmap, GPIO1IRQ, &p1))
283 regmap_write(cg->regmap, GPIO0IRQ, p0);
284 regmap_write(cg->regmap, GPIO1IRQ, p1);
289 virq = irq_find_mapping(cg->chip.irq.domain, gpio);
299 struct crystalcove_gpio *cg = gpiochip_get_data(chip);
304 regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
305 regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
306 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
308 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
310 regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
329 struct crystalcove_gpio *cg;
338 cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
339 if (!cg)
342 platform_set_drvdata(pdev, cg);
344 mutex_init(&cg->buslock);
345 cg->chip.label = KBUILD_MODNAME;
346 cg->chip.direction_input = crystalcove_gpio_dir_in;
347 cg->chip.direction_output = crystalcove_gpio_dir_out;
348 cg->chip.get = crystalcove_gpio_get;
349 cg->chip.set = crystalcove_gpio_set;
350 cg->chip.base = -1;
351 cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
352 cg->chip.can_sleep = true;
353 cg->chip.parent = dev;
354 cg->chip.dbg_show = crystalcove_gpio_dbg_show;
355 cg->regmap = pmic->regmap;
357 girq = &cg->chip.irq;
369 IRQF_ONESHOT, KBUILD_MODNAME, cg);
375 retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);