Lines Matching refs:bank
36 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
37 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
38 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
39 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
40 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
41 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
42 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
43 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
44 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
76 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
77 return bank->parent_priv;
81 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
83 void __iomem *reg_base = bank->parent_priv->reg_base;
85 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
86 bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
90 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
95 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
96 status = __brcmstb_gpio_get_active_irqs(bank);
97 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
103 struct brcmstb_gpio_bank *bank)
105 return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
108 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
111 struct gpio_chip *gc = &bank->gc;
112 struct brcmstb_gpio_priv *priv = bank->parent_priv;
113 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
118 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
123 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
143 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
145 brcmstb_gpio_set_imask(bank, d->hwirq, false);
151 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
153 brcmstb_gpio_set_imask(bank, d->hwirq, true);
159 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
160 struct brcmstb_gpio_priv *priv = bank->parent_priv;
161 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
163 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
169 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
170 struct brcmstb_gpio_priv *priv = bank->parent_priv;
171 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
207 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
209 iedge_config = bank->gc.read_reg(priv->reg_base +
210 GIO_EC(bank->id)) & ~mask;
211 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
212 GIO_EI(bank->id)) & ~mask;
213 ilevel = bank->gc.read_reg(priv->reg_base +
214 GIO_LEVEL(bank->id)) & ~mask;
216 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
218 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
220 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
223 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
245 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
246 struct brcmstb_gpio_priv *priv = bank->parent_priv;
247 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
254 bank->wake_active |= mask;
256 bank->wake_active &= ~mask;
272 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
274 struct brcmstb_gpio_priv *priv = bank->parent_priv;
276 int hwbase = bank->gc.base - priv->gpio_base;
279 while ((status = brcmstb_gpio_get_active_irqs(bank))) {
283 if (offset >= bank->width)
285 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
286 bank->id, offset);
298 struct brcmstb_gpio_bank *bank;
304 list_for_each_entry(bank, &priv->bank_list, node)
305 brcmstb_gpio_irq_bank_handler(bank);
312 struct brcmstb_gpio_bank *bank;
316 list_for_each_entry_reverse(bank, &priv->bank_list, node) {
317 i += bank->gc.ngpio;
319 return bank;
336 struct brcmstb_gpio_bank *bank =
341 if (!bank)
344 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
345 irq, (int)hwirq, bank->id);
346 ret = irq_set_chip_data(irq, &bank->gc);
374 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
377 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
388 struct brcmstb_gpio_bank *bank;
412 list_for_each_entry(bank, &priv->bank_list, node)
413 gpiochip_remove(&bank->gc);
422 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
437 if (unlikely(offset >= bank->width)) {
514 struct brcmstb_gpio_bank *bank)
516 struct gpio_chip *gc = &bank->gc;
520 bank->saved_regs[i] = gc->read_reg(priv->reg_base +
521 GIO_BANK_OFF(bank->id, i));
527 struct brcmstb_gpio_bank *bank;
535 list_for_each_entry(bank, &priv->bank_list, node) {
536 gc = &bank->gc;
539 brcmstb_gpio_bank_save(priv, bank);
543 imask = bank->wake_active;
546 gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
559 struct brcmstb_gpio_bank *bank)
561 struct gpio_chip *gc = &bank->gc;
565 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
566 bank->saved_regs[i]);
578 struct brcmstb_gpio_bank *bank;
581 list_for_each_entry(bank, &priv->bank_list, node) {
582 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
583 brcmstb_gpio_bank_restore(priv, bank);
607 struct brcmstb_gpio_bank *bank)
614 base = bank->id * MAX_GPIO_PER_BANK;
630 for (i = 0; i < bank->width; i++) {
646 bank->gc.names = names;
703 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
705 struct brcmstb_gpio_bank *bank;
709 * If bank_width is 0, then there is an empty bank in the
713 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
720 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
721 if (!bank) {
726 bank->parent_priv = priv;
727 bank->id = num_banks;
729 dev_err(dev, "Invalid bank width %d\n", bank_width);
733 bank->width = bank_width;
740 gc = &bank->gc;
742 reg_base + GIO_DATA(bank->id),
744 reg_base + GIO_IODIR(bank->id), flags);
760 /* not all ngpio lines are valid, will use bank width later */
769 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
770 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
772 brcmstb_gpio_set_names(dev, bank);
773 err = gpiochip_add_data(gc, bank);
775 dev_err(dev, "Could not add gpiochip for bank %d\n",
776 bank->id);
781 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
782 gc->base, gc->ngpio, bank->width);
784 /* Everything looks good, so add bank to list */
785 list_add(&bank->node, &priv->bank_list);