Lines Matching defs:reg_base
67 void __iomem *reg_base;
83 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
86 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
87 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
99 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
101 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
115 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
117 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
125 void __iomem *reg_base = kona_gpio->reg_base;
128 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
135 void __iomem *reg_base;
142 reg_base = kona_gpio->reg_base;
151 val = readl(reg_base + reg_offset);
153 writel(val, reg_base + reg_offset);
162 void __iomem *reg_base;
169 reg_base = kona_gpio->reg_base;
178 val = readl(reg_base + reg_offset);
204 void __iomem *reg_base;
209 reg_base = kona_gpio->reg_base;
212 val = readl(reg_base + GPIO_CONTROL(gpio));
215 writel(val, reg_base + GPIO_CONTROL(gpio));
226 void __iomem *reg_base;
233 reg_base = kona_gpio->reg_base;
236 val = readl(reg_base + GPIO_CONTROL(gpio));
239 writel(val, reg_base + GPIO_CONTROL(gpio));
242 val = readl(reg_base + reg_offset);
244 writel(val, reg_base + reg_offset);
265 void __iomem *reg_base;
270 reg_base = kona_gpio->reg_base;
292 val = readl(reg_base + GPIO_CONTROL(gpio));
303 writel(val, reg_base + GPIO_CONTROL(gpio));
340 void __iomem *reg_base;
348 reg_base = kona_gpio->reg_base;
351 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
353 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
361 void __iomem *reg_base;
369 reg_base = kona_gpio->reg_base;
372 val = readl(reg_base + GPIO_INT_MASK(bank_id));
374 writel(val, reg_base + GPIO_INT_MASK(bank_id));
383 void __iomem *reg_base;
391 reg_base = kona_gpio->reg_base;
394 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
396 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
405 void __iomem *reg_base;
412 reg_base = kona_gpio->reg_base;
437 val = readl(reg_base + GPIO_CONTROL(gpio));
440 writel(val, reg_base + GPIO_CONTROL(gpio));
449 void __iomem *reg_base;
462 reg_base = bank->kona_gpio->reg_base;
465 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
466 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
476 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
477 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
551 void __iomem *reg_base;
554 reg_base = kona_gpio->reg_base;
558 bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
559 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
560 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
562 bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
623 kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
624 if (IS_ERR(kona_gpio->reg_base)) {
625 ret = PTR_ERR(kona_gpio->reg_base);