Lines Matching refs:gpio
10 #include <linux/gpio/driver.h>
11 #include <linux/gpio/aspeed.h>
28 #include <linux/gpio/consumer.h>
208 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio,
214 return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
216 return gpio->base + bank->rdata_reg;
218 return gpio->base + bank->val_regs + GPIO_VAL_DIR;
220 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
222 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
228 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
230 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
232 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
234 return gpio->base + bank->tolerance_regs;
236 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;
238 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;
265 struct aspeed_gpio *gpio, unsigned int offset)
267 const struct aspeed_bank_props *props = gpio->config->props;
278 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
280 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
288 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
290 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
298 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
300 const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
305 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio,
309 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0);
310 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1);
337 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio,
342 if (!copro_ops || !gpio->cf_copro_bankmap)
344 if (!gpio->cf_copro_bankmap[offset >> 3])
353 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM);
356 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata));
361 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio,
366 if (!copro_ops || !gpio->cf_copro_bankmap)
368 if (!gpio->cf_copro_bankmap[offset >> 3])
374 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3,
383 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
386 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset));
392 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
397 addr = bank_reg(gpio, bank, reg_val);
398 reg = gpio->dcache[GPIO_BANK(offset)];
404 gpio->dcache[GPIO_BANK(offset)] = reg;
412 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
416 raw_spin_lock_irqsave(&gpio->lock, flags);
417 copro = aspeed_gpio_copro_request(gpio, offset);
422 aspeed_gpio_copro_release(gpio, offset);
423 raw_spin_unlock_irqrestore(&gpio->lock, flags);
428 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
430 void __iomem *addr = bank_reg(gpio, bank, reg_dir);
435 if (!have_input(gpio, offset))
438 raw_spin_lock_irqsave(&gpio->lock, flags);
443 copro = aspeed_gpio_copro_request(gpio, offset);
446 aspeed_gpio_copro_release(gpio, offset);
448 raw_spin_unlock_irqrestore(&gpio->lock, flags);
456 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
458 void __iomem *addr = bank_reg(gpio, bank, reg_dir);
463 if (!have_output(gpio, offset))
466 raw_spin_lock_irqsave(&gpio->lock, flags);
471 copro = aspeed_gpio_copro_request(gpio, offset);
476 aspeed_gpio_copro_release(gpio, offset);
477 raw_spin_unlock_irqrestore(&gpio->lock, flags);
484 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
489 if (!have_input(gpio, offset))
492 if (!have_output(gpio, offset))
495 raw_spin_lock_irqsave(&gpio->lock, flags);
497 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);
499 raw_spin_unlock_irqrestore(&gpio->lock, flags);
505 struct aspeed_gpio **gpio,
519 *gpio = internal;
529 struct aspeed_gpio *gpio;
536 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
540 status_addr = bank_reg(gpio, bank, reg_irq_status);
542 raw_spin_lock_irqsave(&gpio->lock, flags);
543 copro = aspeed_gpio_copro_request(gpio, offset);
548 aspeed_gpio_copro_release(gpio, offset);
549 raw_spin_unlock_irqrestore(&gpio->lock, flags);
555 struct aspeed_gpio *gpio;
562 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
566 addr = bank_reg(gpio, bank, reg_irq_enable);
568 raw_spin_lock_irqsave(&gpio->lock, flags);
569 copro = aspeed_gpio_copro_request(gpio, offset);
579 aspeed_gpio_copro_release(gpio, offset);
580 raw_spin_unlock_irqrestore(&gpio->lock, flags);
601 struct aspeed_gpio *gpio;
607 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
632 raw_spin_lock_irqsave(&gpio->lock, flags);
633 copro = aspeed_gpio_copro_request(gpio, offset);
635 addr = bank_reg(gpio, bank, reg_irq_type0);
640 addr = bank_reg(gpio, bank, reg_irq_type1);
645 addr = bank_reg(gpio, bank, reg_irq_type2);
651 aspeed_gpio_copro_release(gpio, offset);
652 raw_spin_unlock_irqrestore(&gpio->lock, flags);
666 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
670 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
690 struct aspeed_gpio *gpio = gpiochip_get_data(gc);
691 const struct aspeed_bank_props *props = gpio->config->props;
701 if (i >= gpio->chip.ngpio)
714 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
720 treg = bank_reg(gpio, to_bank(offset), reg_tolerance);
722 raw_spin_lock_irqsave(&gpio->lock, flags);
723 copro = aspeed_gpio_copro_request(gpio, offset);
735 aspeed_gpio_copro_release(gpio, offset);
736 raw_spin_unlock_irqrestore(&gpio->lock, flags);
754 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
761 rate = clk_get_rate(gpio->clk);
777 /* Call under gpio->lock */
778 static int register_allocated_timer(struct aspeed_gpio *gpio,
781 if (WARN(gpio->offset_timer[offset] != 0,
783 offset, gpio->offset_timer[offset]))
786 if (WARN(gpio->timer_users[timer] == UINT_MAX,
790 gpio->offset_timer[offset] = timer;
791 gpio->timer_users[timer]++;
796 /* Call under gpio->lock */
797 static int unregister_allocated_timer(struct aspeed_gpio *gpio,
800 if (WARN(gpio->offset_timer[offset] == 0,
804 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
806 gpio->offset_timer[offset]))
809 gpio->timer_users[gpio->offset_timer[offset]]--;
810 gpio->offset_timer[offset] = 0;
815 /* Call under gpio->lock */
816 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
819 return gpio->offset_timer[offset] > 0;
822 /* Call under gpio->lock */
823 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
834 addr = bank_reg(gpio, bank, reg_debounce_sel1);
838 addr = bank_reg(gpio, bank, reg_debounce_sel2);
846 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
852 if (!gpio->clk)
855 rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
858 usecs, clk_get_rate(gpio->clk), rc);
862 raw_spin_lock_irqsave(&gpio->lock, flags);
864 if (timer_allocation_registered(gpio, offset)) {
865 rc = unregister_allocated_timer(gpio, offset);
874 cycles = ioread32(gpio->base + debounce_timers[i]);
886 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
887 if (gpio->timer_users[j] == 0)
891 if (j == ARRAY_SIZE(gpio->timer_users)) {
904 configure_timer(gpio, offset, 0);
910 iowrite32(requested_cycles, gpio->base + debounce_timers[i]);
918 register_allocated_timer(gpio, offset, i);
919 configure_timer(gpio, offset, i);
922 raw_spin_unlock_irqrestore(&gpio->lock, flags);
929 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
933 raw_spin_lock_irqsave(&gpio->lock, flags);
935 rc = unregister_allocated_timer(gpio, offset);
937 configure_timer(gpio, offset, 0);
939 raw_spin_unlock_irqrestore(&gpio->lock, flags);
947 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
949 if (!have_debounce(gpio, offset))
1008 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
1013 if (!gpio->cf_copro_bankmap)
1014 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL);
1015 if (!gpio->cf_copro_bankmap)
1017 if (offset < 0 || offset > gpio->chip.ngpio)
1021 raw_spin_lock_irqsave(&gpio->lock, flags);
1024 if (gpio->cf_copro_bankmap[bindex] == 0xff) {
1028 gpio->cf_copro_bankmap[bindex]++;
1031 if (gpio->cf_copro_bankmap[bindex] == 1)
1032 aspeed_gpio_change_cmd_source(gpio, bank, bindex,
1042 raw_spin_unlock_irqrestore(&gpio->lock, flags);
1054 struct aspeed_gpio *gpio = gpiochip_get_data(chip);
1059 if (!gpio->cf_copro_bankmap)
1062 if (offset < 0 || offset > gpio->chip.ngpio)
1066 raw_spin_lock_irqsave(&gpio->lock, flags);
1069 if (gpio->cf_copro_bankmap[bindex] == 0) {
1073 gpio->cf_copro_bankmap[bindex]--;
1076 if (gpio->cf_copro_bankmap[bindex] == 0)
1077 aspeed_gpio_change_cmd_source(gpio, bank, bindex,
1080 raw_spin_unlock_irqrestore(&gpio->lock, flags);
1132 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1133 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1134 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1142 struct aspeed_gpio *gpio;
1146 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
1147 if (!gpio)
1150 gpio->base = devm_platform_ioremap_resource(pdev, 0);
1151 if (IS_ERR(gpio->base))
1152 return PTR_ERR(gpio->base);
1154 raw_spin_lock_init(&gpio->lock);
1160 gpio->clk = of_clk_get(pdev->dev.of_node, 0);
1161 if (IS_ERR(gpio->clk)) {
1164 gpio->clk = NULL;
1167 gpio->config = gpio_id->data;
1169 gpio->chip.parent = &pdev->dev;
1171 gpio->chip.ngpio = (u16) ngpio;
1173 gpio->chip.ngpio = gpio->config->nr_gpios;
1174 gpio->chip.direction_input = aspeed_gpio_dir_in;
1175 gpio->chip.direction_output = aspeed_gpio_dir_out;
1176 gpio->chip.get_direction = aspeed_gpio_get_direction;
1177 gpio->chip.request = aspeed_gpio_request;
1178 gpio->chip.free = aspeed_gpio_free;
1179 gpio->chip.get = aspeed_gpio_get;
1180 gpio->chip.set = aspeed_gpio_set;
1181 gpio->chip.set_config = aspeed_gpio_set_config;
1182 gpio->chip.label = dev_name(&pdev->dev);
1183 gpio->chip.base = -1;
1186 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
1187 gpio->dcache = devm_kcalloc(&pdev->dev,
1189 if (!gpio->dcache)
1198 void __iomem *addr = bank_reg(gpio, bank, reg_rdata);
1199 gpio->dcache[i] = ioread32(addr);
1200 aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM);
1201 aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM);
1202 aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM);
1203 aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM);
1211 gpio->irq = rc;
1212 girq = &gpio->chip.irq;
1213 girq->chip = &gpio->irqc;
1226 girq->parents[0] = gpio->irq;
1232 gpio->offset_timer =
1233 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
1234 if (!gpio->offset_timer)
1237 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);