Lines Matching refs:ctrl_base
34 static const u32 ctrl_base = 0x80000000;
220 opb_readl(aspeed, ctrl_base + FSI_MRESP0, &mresp0);
221 opb_readl(aspeed, ctrl_base + FSI_MSTAP0, &mstap0);
222 opb_readl(aspeed, ctrl_base + FSI_MESRB0, &mesrb0);
234 ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0,
332 ret = opb_writel(aspeed, ctrl_base + FSI_MCENP0 + (4 * idx), reg);
336 ret = opb_writel(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), reg);
393 opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);
398 opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);
401 opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg);
409 opb_writel(aspeed, ctrl_base + FSI_MMODE, reg);
412 opb_writel(aspeed, ctrl_base + FSI_MDLYR, reg);
415 opb_writel(aspeed, ctrl_base + FSI_MSENP0, reg);
420 opb_writel(aspeed, ctrl_base + FSI_MCENP0, reg);
422 opb_readl(aspeed, ctrl_base + FSI_MAEB, NULL);
425 opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);
427 opb_readl(aspeed, ctrl_base + FSI_MLEVP0, NULL);
431 opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);
434 opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);
449 opb_writel(aspeed, ctrl_base + FSI_MRESP0, cpu_to_be32(FSI_MRESP_RST_ALL_MASTER));
575 writel(ctrl_base, aspeed->base + OPB_CTRL_BASE);
592 rc = opb_readl(aspeed, ctrl_base + FSI_MVER, &raw);