Lines Matching refs:base
137 * @ioaddr: mapped base address of mmio region.
299 void __iomem *base = priv->ioaddr;
301 return fme_read_perf_cntr_reg(base + CLK_CNTR);
316 void __iomem *base = priv->ioaddr;
328 v = readq(base + CACHE_CTRL);
332 writeq(v, base + CACHE_CTRL);
334 if (readq_poll_timeout_atomic(base + CACHE_CNTR0, v,
341 v = fme_read_perf_cntr_reg(base + CACHE_CNTR0);
343 v = fme_read_perf_cntr_reg(base + CACHE_CNTR1);
365 void __iomem *base = priv->ioaddr;
398 v = readq(base + FAB_CTRL);
407 writeq(v, base + FAB_CTRL);
425 void __iomem *base = priv->ioaddr;
428 v = readq(base + FAB_CTRL);
431 writeq(v, base + FAB_CTRL);
433 if (readq_poll_timeout_atomic(base + FAB_CNTR, v,
440 v = fme_read_perf_cntr_reg(base + FAB_CNTR);
456 void __iomem *base = priv->ioaddr;
461 v = readq(base + VTD_CTRL);
464 writeq(v, base + VTD_CTRL);
466 if (readq_poll_timeout_atomic(base + VTD_CNTR, v,
473 v = fme_read_perf_cntr_reg(base + VTD_CNTR);
489 void __iomem *base = priv->ioaddr;
492 v = readq(base + VTD_SIP_CTRL);
495 writeq(v, base + VTD_SIP_CTRL);
497 if (readq_poll_timeout_atomic(base + VTD_SIP_CNTR, v,
504 v = fme_read_perf_cntr_reg(base + VTD_SIP_CNTR);
892 void __iomem *base = priv->ioaddr;
896 v = readq(base + FAB_CTRL);