Lines Matching defs:base
46 void __iomem *base;
49 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
52 value = readq(base + PCIE0_ERROR);
63 void __iomem *base;
70 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
73 writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK);
75 v = readq(base + PCIE0_ERROR);
77 writeq(v, base + PCIE0_ERROR);
81 writeq(0ULL, base + PCIE0_ERROR_MASK);
91 void __iomem *base;
94 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
97 value = readq(base + PCIE1_ERROR);
108 void __iomem *base;
115 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
118 writeq(GENMASK_ULL(63, 0), base + PCIE1_ERROR_MASK);
120 v = readq(base + PCIE1_ERROR);
122 writeq(v, base + PCIE1_ERROR);
126 writeq(0ULL, base + PCIE1_ERROR_MASK);
135 void __iomem *base;
137 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
140 (unsigned long long)readq(base + RAS_NONFAT_ERROR));
147 void __iomem *base;
149 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
152 (unsigned long long)readq(base + RAS_CATFAT_ERROR));
160 void __iomem *base;
163 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
166 v = readq(base + RAS_ERROR_INJECT);
178 void __iomem *base;
188 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
191 v = readq(base + RAS_ERROR_INJECT);
194 writeq(v, base + RAS_ERROR_INJECT);
205 void __iomem *base;
208 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
211 value = readq(base + FME_ERROR);
222 void __iomem *base;
229 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
232 writeq(GENMASK_ULL(63, 0), base + FME_ERROR_MASK);
234 v = readq(base + FME_ERROR);
236 writeq(v, base + FME_ERROR);
241 writeq(dfl_feature_revision(base) ? 0ULL : MBP_ERROR,
242 base + FME_ERROR_MASK);
252 void __iomem *base;
255 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
258 value = readq(base + FME_FIRST_ERROR);
269 void __iomem *base;
272 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
275 value = readq(base + FME_NEXT_ERROR);
318 void __iomem *base;
320 base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
325 if (dfl_feature_revision(base))
326 writeq(mask ? ERROR_MASK : 0, base + FME_ERROR_MASK);
328 writeq(mask ? ERROR_MASK : MBP_ERROR, base + FME_ERROR_MASK);
330 writeq(mask ? ERROR_MASK : 0, base + PCIE0_ERROR_MASK);
331 writeq(mask ? ERROR_MASK : 0, base + PCIE1_ERROR_MASK);
332 writeq(mask ? ERROR_MASK : 0, base + RAS_NONFAT_ERROR_MASK);
333 writeq(mask ? ERROR_MASK : 0, base + RAS_CATFAT_ERROR_MASK);