Lines Matching refs:tx
48 * written through the tx.channel pointer, while the second is only written
62 } tx;
97 u32 tx = READ_ONCE(header->tx.count);
110 if (tx - rx > ivc->num_frames)
113 return tx == rx;
119 u32 tx = READ_ONCE(header->tx.count);
126 return tx - rx >= ivc->num_frames;
132 u32 tx = READ_ONCE(header->tx.count);
141 return tx - rx;
146 WRITE_ONCE(ivc->tx.channel->tx.count,
147 READ_ONCE(ivc->tx.channel->tx.count) + 1);
149 if (ivc->tx.position == ivc->num_frames - 1)
150 ivc->tx.position = 0;
152 ivc->tx.position++;
168 unsigned int offset = offsetof(struct tegra_ivc_header, tx.count);
171 * tx.channel->state is set locally, so it is not synchronized with
178 if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED)
203 if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED)
206 if (!tegra_ivc_full(ivc, ivc->tx.channel))
209 tegra_ivc_invalidate(ivc, ivc->tx.phys + offset);
211 if (tegra_ivc_full(ivc, ivc->tx.channel))
294 unsigned int tx = offsetof(struct tegra_ivc_header, tx.count);
312 * ivc->tx.position.
321 tegra_ivc_invalidate(ivc, ivc->rx.phys + tx);
330 /* directly poke at the next frame to be tx'ed */
339 return tegra_ivc_frame_virt(ivc, ivc->tx.channel, ivc->tx.position);
343 /* advance the tx buffer */
346 unsigned int tx = offsetof(struct tegra_ivc_header, tx.count);
354 tegra_ivc_flush_frame(ivc, ivc->tx.phys, ivc->tx.position, 0,
359 * ivc->tx.position.
364 tegra_ivc_flush(ivc, ivc->tx.phys + tx);
367 * Ensure our write to ivc->tx.position occurs before our read from
377 tegra_ivc_invalidate(ivc, ivc->tx.phys + rx);
379 if (tegra_ivc_available(ivc, ivc->tx.channel) == 1)
388 unsigned int offset = offsetof(struct tegra_ivc_header, tx.count);
390 ivc->tx.channel->tx.state = TEGRA_IVC_STATE_SYNC;
391 tegra_ivc_flush(ivc, ivc->tx.phys + offset);
418 unsigned int offset = offsetof(struct tegra_ivc_header, tx.count);
423 state = READ_ONCE(ivc->rx.channel->tx.state);
426 offset = offsetof(struct tegra_ivc_header, tx.count);
430 * clearing tx.channel.
435 * Reset tx.channel counters. The remote end is in the SYNC
439 ivc->tx.channel->tx.count = 0;
442 ivc->tx.position = 0;
455 ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ACK;
456 tegra_ivc_flush(ivc, ivc->tx.phys + offset);
463 } else if (ivc->tx.channel->tx.state == TEGRA_IVC_STATE_SYNC &&
465 offset = offsetof(struct tegra_ivc_header, tx.count);
474 * Reset tx.channel counters. The remote end is in the ACK
478 ivc->tx.channel->tx.count = 0;
481 ivc->tx.position = 0;
495 ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ESTABLISHED;
496 tegra_ivc_flush(ivc, ivc->tx.phys + offset);
503 } else if (ivc->tx.channel->tx.state == TEGRA_IVC_STATE_ACK) {
504 offset = offsetof(struct tegra_ivc_header, tx.count);
509 * peer state before storing to tx.channel.
519 ivc->tx.channel->tx.state = TEGRA_IVC_STATE_ESTABLISHED;
520 tegra_ivc_flush(ivc, ivc->tx.phys + offset);
536 if (ivc->tx.channel->tx.state != TEGRA_IVC_STATE_ESTABLISHED)
561 static int tegra_ivc_check_params(unsigned long rx, unsigned long tx,
564 BUILD_BUG_ON(!IS_ALIGNED(offsetof(struct tegra_ivc_header, tx.count),
590 if (!IS_ALIGNED(tx, TEGRA_IVC_ALIGN)) {
591 pr_err("IVC channel start not aligned: %#lx\n", tx);
595 if (rx < tx) {
596 if (rx + frame_size * num_frames > tx) {
598 rx, frame_size * num_frames, tx);
602 if (tx + frame_size * num_frames > rx) {
604 tx, frame_size * num_frames, rx);
613 dma_addr_t rx_phys, void *tx, dma_addr_t tx_phys,
631 err = tegra_ivc_check_params((unsigned long)rx, (unsigned long)tx,
644 ivc->tx.phys = dma_map_single(peer, tx, queue_size,
646 if (dma_mapping_error(peer, ivc->tx.phys)) {
653 ivc->tx.phys = tx_phys;
657 ivc->tx.channel = tx;
668 ivc->tx.position = 0;
683 dma_unmap_single(ivc->peer, ivc->tx.phys, size,