Lines Matching refs:rx
49 * through the rx.channel pointer. This delineates ownership of the cache
68 } rx;
98 u32 rx = READ_ONCE(header->rx.count);
110 if (tx - rx > ivc->num_frames)
113 return tx == rx;
120 u32 rx = READ_ONCE(header->rx.count);
126 return tx - rx >= ivc->num_frames;
133 u32 rx = READ_ONCE(header->rx.count);
141 return tx - rx;
157 WRITE_ONCE(ivc->rx.channel->rx.count,
158 READ_ONCE(ivc->rx.channel->rx.count) + 1);
160 if (ivc->rx.position == ivc->num_frames - 1)
161 ivc->rx.position = 0;
163 ivc->rx.position++;
175 * asynchronous transition of rx.channel->state to
188 if (!tegra_ivc_empty(ivc, ivc->rx.channel))
191 tegra_ivc_invalidate(ivc, ivc->rx.phys + offset);
193 if (tegra_ivc_empty(ivc, ivc->rx.channel))
201 unsigned int offset = offsetof(struct tegra_ivc_header, rx.count);
266 /* directly peek at the next frame rx'ed */
279 * Order observation of ivc->rx.position potentially indicating new
284 tegra_ivc_invalidate_frame(ivc, ivc->rx.phys, ivc->rx.position, 0,
287 return tegra_ivc_frame_virt(ivc, ivc->rx.channel, ivc->rx.position);
293 unsigned int rx = offsetof(struct tegra_ivc_header, rx.count);
308 tegra_ivc_flush(ivc, ivc->rx.phys + rx);
311 * Ensure our write to ivc->rx.position occurs before our read from
321 tegra_ivc_invalidate(ivc, ivc->rx.phys + tx);
323 if (tegra_ivc_available(ivc, ivc->rx.channel) == ivc->num_frames - 1)
347 unsigned int rx = offsetof(struct tegra_ivc_header, rx.count);
368 * ivc->rx.position.
377 tegra_ivc_invalidate(ivc, ivc->tx.phys + rx);
422 tegra_ivc_invalidate(ivc, ivc->rx.phys + offset);
423 state = READ_ONCE(ivc->rx.channel->tx.state);
440 ivc->rx.channel->rx.count = 0;
443 ivc->rx.position = 0;
479 ivc->rx.channel->rx.count = 0;
482 ivc->rx.position = 0;
561 static int tegra_ivc_check_params(unsigned long rx, unsigned long tx,
566 BUILD_BUG_ON(!IS_ALIGNED(offsetof(struct tegra_ivc_header, rx.count),
585 if (!IS_ALIGNED(rx, TEGRA_IVC_ALIGN)) {
586 pr_err("IVC channel start not aligned: %#lx\n", rx);
595 if (rx < tx) {
596 if (rx + frame_size * num_frames > tx) {
598 rx, frame_size * num_frames, tx);
602 if (tx + frame_size * num_frames > rx) {
604 tx, frame_size * num_frames, rx);
612 int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, void *rx,
631 err = tegra_ivc_check_params((unsigned long)rx, (unsigned long)tx,
639 ivc->rx.phys = dma_map_single(peer, rx, queue_size,
641 if (dma_mapping_error(peer, ivc->rx.phys))
647 dma_unmap_single(peer, ivc->rx.phys, queue_size,
652 ivc->rx.phys = rx_phys;
656 ivc->rx.channel = rx;
669 ivc->rx.position = 0;
681 dma_unmap_single(ivc->peer, ivc->rx.phys, size,