Lines Matching refs:reg_write
572 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
599 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
625 reg_write(ohci, OHCI1394_PhyControl,
717 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
739 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1076 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1077 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1255 reg_write(ohci, COMMAND_PTR(ctx->regs),
1257 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1258 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1305 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1452 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1611 reg_write(ohci, OHCI1394_CSRData, lock_data);
1612 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1613 reg_write(ohci, OHCI1394_CSRControl, sel);
1798 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1946 reg_write(ohci, OHCI1394_LinkControlSet,
2051 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2080 reg_write(ohci, OHCI1394_BusOptions,
2083 reg_write(ohci, OHCI1394_ConfigROMhdr,
2088 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2089 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2121 reg_write(ohci, OHCI1394_IntEventClear,
2142 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2154 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2170 reg_write(ohci, OHCI1394_IntEventClear,
2179 reg_write(ohci, OHCI1394_LinkControlSet,
2212 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2278 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2281 reg_write(ohci, OHCI1394_HCControlClear,
2335 reg_write(ohci, OHCI1394_HCControlSet,
2361 reg_write(ohci, OHCI1394_HCControlClear,
2364 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2365 reg_write(ohci, OHCI1394_LinkControlSet,
2369 reg_write(ohci, OHCI1394_ATRetries,
2379 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2384 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2390 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2392 reg_write(ohci, OHCI1394_FairnessControl, 0);
2395 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
2396 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2397 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2447 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2448 reg_write(ohci, OHCI1394_BusOptions,
2450 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2452 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2466 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2468 reg_write(ohci, OHCI1394_HCControlSet,
2472 reg_write(ohci, OHCI1394_LinkControlSet,
2553 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2645 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2647 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2715 reg_write(ohci, OHCI1394_LinkControlClear,
2725 reg_write(ohci, OHCI1394_LinkControlSet,
2734 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2739 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2740 reg_write(ohci, OHCI1394_IntEventSet,
2755 reg_write(ohci, OHCI1394_ATRetries, value);
2760 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2969 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2970 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2971 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2972 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
3094 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3095 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3110 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3111 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3112 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3133 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3139 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3508 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3705 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3708 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3714 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3721 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3805 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3880 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3881 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));