Lines Matching refs:ohci
42 #include "ohci.h"
44 #define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args)
45 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args)
46 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args)
88 struct fw_ohci *ohci;
118 struct fw_ohci *ohci;
291 static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci)
293 return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ);
323 #define has_reboot_by_cycle_timer_read_quirk(ohci) false
411 static void log_irqs(struct fw_ohci *ohci, u32 evt)
421 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
460 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
467 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
468 self_id_count, generation, ohci->node_id);
470 for (s = ohci->self_id_buffer; self_id_count--; ++s)
472 ohci_notice(ohci,
479 ohci_notice(ohci,
516 static void log_ar_at_event(struct fw_ohci *ohci,
529 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
549 ohci_notice(ohci, "A%c %s, %s\n",
553 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
557 ohci_notice(ohci,
564 ohci_notice(ohci,
572 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
574 writel(data, ohci->registers + offset);
577 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
579 return readl(ohci->registers + offset);
582 static inline void flush_writes(const struct fw_ohci *ohci)
585 reg_read(ohci, OHCI1394_Version);
590 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
594 static int read_phy_reg(struct fw_ohci *ohci, int addr)
599 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
601 val = reg_read(ohci, OHCI1394_PhyControl);
615 ohci_err(ohci, "failed to read phy reg %d\n", addr);
621 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
625 reg_write(ohci, OHCI1394_PhyControl,
628 val = reg_read(ohci, OHCI1394_PhyControl);
638 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
644 static int update_phy_reg(struct fw_ohci *ohci, int addr,
647 int ret = read_phy_reg(ohci, addr);
658 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
661 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
665 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
669 return read_phy_reg(ohci, addr);
674 struct fw_ohci *ohci = fw_ohci(card);
677 mutex_lock(&ohci->phy_reg_mutex);
678 ret = read_phy_reg(ohci, addr);
679 mutex_unlock(&ohci->phy_reg_mutex);
687 struct fw_ohci *ohci = fw_ohci(card);
690 mutex_lock(&ohci->phy_reg_mutex);
691 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
692 mutex_unlock(&ohci->phy_reg_mutex);
717 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
722 struct device *dev = ctx->ohci->card.device;
736 struct fw_ohci *ohci = ctx->ohci;
738 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
739 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
740 flush_writes(ohci);
742 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
824 dma_sync_single_for_cpu(ctx->ohci->card.device,
830 dma_sync_single_for_cpu(ctx->ohci->card.device,
837 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
844 struct fw_ohci *ohci = ctx->ohci;
903 p.generation = ohci->request_generation;
905 log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
929 if (!(ohci->quirks & QUIRK_RESET_PACKET))
930 ohci->request_generation = (p.header[2] >> 16) & 0xff;
931 } else if (ctx == &ohci->ar_request_ctx) {
932 fw_core_handle_request(&ohci->card, &p);
934 fw_core_handle_response(&ohci->card, &p);
960 dma_sync_single_for_device(ctx->ohci->card.device,
1014 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
1017 struct device *dev = ohci->card.device;
1024 ctx->ohci = ohci;
1045 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
1046 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1076 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1077 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1128 spin_lock_irqsave(&ctx->ohci->lock, flags);
1130 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1138 * context. Must be called with ohci->lock held.
1153 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1175 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1178 ctx->ohci = ohci;
1210 struct fw_card *card = &ctx->ohci->card;
1219 /* Must be called with ohci->lock held */
1253 struct fw_ohci *ohci = ctx->ohci;
1255 reg_write(ohci, COMMAND_PTR(ctx->regs),
1257 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1258 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1260 flush_writes(ohci);
1288 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1301 struct fw_ohci *ohci = ctx->ohci;
1305 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1309 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1316 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
1332 struct fw_ohci *ohci = ctx->ohci;
1411 payload_bus = dma_map_single(ohci->card.device,
1415 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1441 if (ohci->generation != packet->generation) {
1443 dma_unmap_single(ohci->card.device, payload_bus,
1452 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1476 struct fw_ohci *ohci = context->ohci;
1490 dma_unmap_single(ohci->card.device, packet->payload_bus,
1496 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1546 packet->callback(packet, &ohci->card, packet->ack);
1557 static void handle_local_rom(struct fw_ohci *ohci,
1578 (void *) ohci->config_rom + i, length);
1581 fw_core_handle_response(&ohci->card, &response);
1584 static void handle_local_lock(struct fw_ohci *ohci,
1611 reg_write(ohci, OHCI1394_CSRData, lock_data);
1612 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1613 reg_write(ohci, OHCI1394_CSRControl, sel);
1616 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1617 lock_old = cpu_to_be32(reg_read(ohci,
1625 ohci_err(ohci, "swap not done (CSR lock timeout)\n");
1629 fw_core_handle_response(&ohci->card, &response);
1636 if (ctx == &ctx->ohci->at_request_ctx) {
1638 packet->callback(packet, &ctx->ohci->card, packet->ack);
1649 handle_local_rom(ctx->ohci, packet, csr);
1655 handle_local_lock(ctx->ohci, packet, csr);
1658 if (ctx == &ctx->ohci->at_request_ctx)
1659 fw_core_handle_request(&ctx->ohci->card, packet);
1661 fw_core_handle_response(&ctx->ohci->card, packet);
1665 if (ctx == &ctx->ohci->at_response_ctx) {
1667 packet->callback(packet, &ctx->ohci->card, packet->ack);
1676 spin_lock_irqsave(&ctx->ohci->lock, flags);
1678 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1679 ctx->ohci->generation == packet->generation) {
1680 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1686 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1689 packet->callback(packet, &ctx->ohci->card, packet->ack);
1693 static void detect_dead_context(struct fw_ohci *ohci,
1698 ctl = reg_read(ohci, CONTROL_SET(regs));
1700 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
1704 static void handle_dead_contexts(struct fw_ohci *ohci)
1709 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1710 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1711 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1712 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1714 if (!(ohci->it_context_support & (1 << i)))
1717 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1720 if (!(ohci->ir_context_support & (1 << i)))
1723 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1754 static u32 get_cycle_time(struct fw_ohci *ohci)
1761 if (has_reboot_by_cycle_timer_read_quirk(ohci))
1764 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1766 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1769 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1773 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1793 static u32 update_bus_time(struct fw_ohci *ohci)
1795 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1797 if (unlikely(!ohci->bus_time_running)) {
1798 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1799 ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) |
1801 ohci->bus_time_running = true;
1804 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1805 ohci->bus_time += 0x40;
1807 return ohci->bus_time | cycle_time_seconds;
1810 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1814 mutex_lock(&ohci->phy_reg_mutex);
1815 reg = write_phy_reg(ohci, 7, port_index);
1817 reg = read_phy_reg(ohci, 8);
1818 mutex_unlock(&ohci->phy_reg_mutex);
1831 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1838 entry = ohci->self_id_buffer[i];
1847 static int initiated_reset(struct fw_ohci *ohci)
1852 mutex_lock(&ohci->phy_reg_mutex);
1853 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1855 reg = read_phy_reg(ohci, 8);
1857 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1859 reg = read_phy_reg(ohci, 12); /* read register 12 */
1868 mutex_unlock(&ohci->phy_reg_mutex);
1877 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1883 reg = reg_read(ohci, OHCI1394_NodeID);
1885 ohci_notice(ohci,
1891 reg = ohci_read_phy_reg(&ohci->card, 4);
1896 reg = ohci_read_phy_reg(&ohci->card, 1);
1902 status = get_status_for_port(ohci, i);
1908 self_id |= initiated_reset(ohci);
1910 pos = get_self_id_pos(ohci, self_id, self_id_count);
1912 memmove(&(ohci->self_id_buffer[pos+1]),
1913 &(ohci->self_id_buffer[pos]),
1914 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1915 ohci->self_id_buffer[pos] = self_id;
1923 struct fw_ohci *ohci =
1931 reg = reg_read(ohci, OHCI1394_NodeID);
1933 ohci_notice(ohci,
1938 ohci_notice(ohci, "malconfigured bus\n");
1941 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1945 if (!(ohci->is_root && is_new_root))
1946 reg_write(ohci, OHCI1394_LinkControlSet,
1948 ohci->is_root = is_new_root;
1950 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1952 ohci_notice(ohci, "self ID receive error\n");
1964 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
1968 generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
1972 u32 id = cond_le32_to_cpu(ohci->self_id[i]);
1973 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
1984 ohci_notice(ohci, "ignoring spurious self IDs\n");
1989 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
1993 ohci->self_id_buffer[j] = id;
1996 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1997 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1999 ohci_notice(ohci,
2006 ohci_notice(ohci, "no self IDs\n");
2025 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
2027 ohci_notice(ohci, "new bus reset, discarding self ids\n");
2032 spin_lock_irq(&ohci->lock);
2034 ohci->generation = -1; /* prevent AT packet queueing */
2035 context_stop(&ohci->at_request_ctx);
2036 context_stop(&ohci->at_response_ctx);
2038 spin_unlock_irq(&ohci->lock);
2045 at_context_flush(&ohci->at_request_ctx);
2046 at_context_flush(&ohci->at_response_ctx);
2048 spin_lock_irq(&ohci->lock);
2050 ohci->generation = generation;
2051 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2053 if (ohci->quirks & QUIRK_RESET_PACKET)
2054 ohci->request_generation = generation;
2065 if (ohci->next_config_rom != NULL) {
2066 if (ohci->next_config_rom != ohci->config_rom) {
2067 free_rom = ohci->config_rom;
2068 free_rom_bus = ohci->config_rom_bus;
2070 ohci->config_rom = ohci->next_config_rom;
2071 ohci->config_rom_bus = ohci->next_config_rom_bus;
2072 ohci->next_config_rom = NULL;
2080 reg_write(ohci, OHCI1394_BusOptions,
2081 be32_to_cpu(ohci->config_rom[2]));
2082 ohci->config_rom[0] = ohci->next_header;
2083 reg_write(ohci, OHCI1394_ConfigROMhdr,
2084 be32_to_cpu(ohci->next_header));
2088 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2089 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2092 spin_unlock_irq(&ohci->lock);
2095 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2098 log_selfids(ohci, generation, self_id_count);
2100 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2101 self_id_count, ohci->self_id_buffer,
2102 ohci->csr_state_setclear_abdicate);
2103 ohci->csr_state_setclear_abdicate = false;
2108 struct fw_ohci *ohci = data;
2112 event = reg_read(ohci, OHCI1394_IntEventClear);
2121 reg_write(ohci, OHCI1394_IntEventClear,
2123 log_irqs(ohci, event);
2126 queue_work(selfid_workqueue, &ohci->bus_reset_work);
2129 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2132 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2135 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2138 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2141 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2142 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2147 &ohci->ir_context_list[i].context.tasklet);
2153 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2154 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2159 &ohci->it_context_list[i].context.tasklet);
2165 ohci_err(ohci, "register access failure\n");
2168 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2169 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2170 reg_write(ohci, OHCI1394_IntEventClear,
2173 ohci_err(ohci, "PCI posted write error\n");
2178 ohci_notice(ohci, "isochronous cycle too long\n");
2179 reg_write(ohci, OHCI1394_LinkControlSet,
2191 ohci_notice(ohci, "isochronous cycle inconsistent\n");
2195 handle_dead_contexts(ohci);
2198 spin_lock(&ohci->lock);
2199 update_bus_time(ohci);
2200 spin_unlock(&ohci->lock);
2202 flush_writes(ohci);
2207 static int software_reset(struct fw_ohci *ohci)
2212 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2214 val = reg_read(ohci, OHCI1394_HCControlSet);
2236 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2242 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2248 ret = read_phy_reg(ohci, 2);
2252 ret = read_paged_phy_reg(ohci, 1, 8);
2259 if (ohci->quirks & QUIRK_NO_1394A)
2270 ret = update_phy_reg(ohci, 5, clear, set);
2278 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2281 reg_write(ohci, OHCI1394_HCControlClear,
2287 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2293 reg = read_phy_reg(ohci, 2);
2300 reg = read_paged_phy_reg(ohci, 1, i + 10);
2312 struct fw_ohci *ohci = fw_ohci(card);
2316 ret = software_reset(ohci);
2318 ohci_err(ohci, "failed to reset ohci card\n");
2335 reg_write(ohci, OHCI1394_HCControlSet,
2338 flush_writes(ohci);
2342 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2347 ohci_err(ohci, "failed to set Link Power Status\n");
2351 if (ohci->quirks & QUIRK_TI_SLLZ059) {
2352 ret = probe_tsb41ba3d(ohci);
2356 ohci_notice(ohci, "local TSB41BA3D phy\n");
2358 ohci->quirks &= ~QUIRK_TI_SLLZ059;
2361 reg_write(ohci, OHCI1394_HCControlClear,
2364 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2365 reg_write(ohci, OHCI1394_LinkControlSet,
2369 reg_write(ohci, OHCI1394_ATRetries,
2375 ohci->bus_time_running = false;
2378 if (ohci->ir_context_support & (1 << i))
2379 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2382 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2384 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2390 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2391 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2392 reg_write(ohci, OHCI1394_FairnessControl, 0);
2393 card->priority_budget_implemented = ohci->pri_req_max != 0;
2395 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
2396 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2397 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2399 ret = configure_1394a_enhancements(ohci);
2428 ohci->next_config_rom =
2429 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2430 &ohci->next_config_rom_bus,
2432 if (ohci->next_config_rom == NULL)
2435 copy_config_rom(ohci->next_config_rom, config_rom, length);
2441 ohci->next_config_rom = ohci->config_rom;
2442 ohci->next_config_rom_bus = ohci->config_rom_bus;
2445 ohci->next_header = ohci->next_config_rom[0];
2446 ohci->next_config_rom[0] = 0;
2447 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2448 reg_write(ohci, OHCI1394_BusOptions,
2449 be32_to_cpu(ohci->next_config_rom[2]));
2450 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2452 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2466 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2468 reg_write(ohci, OHCI1394_HCControlSet,
2472 reg_write(ohci, OHCI1394_LinkControlSet,
2476 ar_context_run(&ohci->ar_request_ctx);
2477 ar_context_run(&ohci->ar_response_ctx);
2479 flush_writes(ohci);
2482 fw_schedule_bus_reset(&ohci->card, false, true);
2490 struct fw_ohci *ohci;
2494 ohci = fw_ohci(card);
2519 * We use ohci->lock to avoid racing with the code that sets
2520 * ohci->next_config_rom to NULL (see bus_reset_work).
2524 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2529 spin_lock_irq(&ohci->lock);
2533 * push our new allocation into the ohci->next_config_rom
2542 if (ohci->next_config_rom == NULL) {
2543 ohci->next_config_rom = next_config_rom;
2544 ohci->next_config_rom_bus = next_config_rom_bus;
2548 copy_config_rom(ohci->next_config_rom, config_rom, length);
2550 ohci->next_header = config_rom[0];
2551 ohci->next_config_rom[0] = 0;
2553 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2555 spin_unlock_irq(&ohci->lock);
2559 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2570 fw_schedule_bus_reset(&ohci->card, true, true);
2577 struct fw_ohci *ohci = fw_ohci(card);
2579 at_context_transmit(&ohci->at_request_ctx, packet);
2584 struct fw_ohci *ohci = fw_ohci(card);
2586 at_context_transmit(&ohci->at_response_ctx, packet);
2591 struct fw_ohci *ohci = fw_ohci(card);
2592 struct context *ctx = &ohci->at_request_ctx;
2602 dma_unmap_single(ohci->card.device, packet->payload_bus,
2605 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2608 packet->callback(packet, &ohci->card, packet->ack);
2619 struct fw_ohci *ohci = fw_ohci(card);
2631 spin_lock_irqsave(&ohci->lock, flags);
2633 if (ohci->generation != generation) {
2645 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2647 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2649 flush_writes(ohci);
2651 spin_unlock_irqrestore(&ohci->lock, flags);
2658 struct fw_ohci *ohci = fw_ohci(card);
2665 if (ohci->is_root &&
2666 (reg_read(ohci, OHCI1394_LinkControlSet) &
2671 if (ohci->csr_state_setclear_abdicate)
2677 return reg_read(ohci, OHCI1394_NodeID) << 16;
2680 return get_cycle_time(ohci);
2688 spin_lock_irqsave(&ohci->lock, flags);
2689 value = update_bus_time(ohci);
2690 spin_unlock_irqrestore(&ohci->lock, flags);
2694 value = reg_read(ohci, OHCI1394_ATRetries);
2698 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2699 (ohci->pri_req_max << 8);
2709 struct fw_ohci *ohci = fw_ohci(card);
2714 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2715 reg_write(ohci, OHCI1394_LinkControlClear,
2717 flush_writes(ohci);
2720 ohci->csr_state_setclear_abdicate = false;
2724 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2725 reg_write(ohci, OHCI1394_LinkControlSet,
2727 flush_writes(ohci);
2730 ohci->csr_state_setclear_abdicate = true;
2734 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2735 flush_writes(ohci);
2739 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2740 reg_write(ohci, OHCI1394_IntEventSet,
2742 flush_writes(ohci);
2746 spin_lock_irqsave(&ohci->lock, flags);
2747 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2749 spin_unlock_irqrestore(&ohci->lock, flags);
2755 reg_write(ohci, OHCI1394_ATRetries, value);
2756 flush_writes(ohci);
2760 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2761 flush_writes(ohci);
2824 dma_sync_single_range_for_cpu(context->ohci->card.device,
2863 dma_sync_single_range_for_cpu(context->ohci->card.device,
2880 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2918 dma_sync_single_range_for_cpu(context->ohci->card.device,
2965 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2969 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2970 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2971 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2972 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2973 ohci->mc_channels = channels;
2979 struct fw_ohci *ohci = fw_ohci(card);
2986 spin_lock_irq(&ohci->lock);
2990 mask = &ohci->it_context_mask;
2996 ctx = &ohci->it_context_list[index];
3001 channels = &ohci->ir_context_channels;
3002 mask = &ohci->ir_context_mask;
3009 ctx = &ohci->ir_context_list[index];
3014 mask = &ohci->ir_context_mask;
3016 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
3018 ohci->mc_allocated = true;
3021 ctx = &ohci->ir_context_list[index];
3030 spin_unlock_irq(&ohci->lock);
3042 ret = context_init(&ctx->context, ohci, regs, callback);
3047 set_multichannel_mask(ohci, 0);
3056 spin_lock_irq(&ohci->lock);
3064 ohci->mc_allocated = false;
3069 spin_unlock_irq(&ohci->lock);
3078 struct fw_ohci *ohci = ctx->context.ohci;
3088 index = ctx - ohci->it_context_list;
3094 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3095 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3103 index = ctx - ohci->ir_context_list;
3110 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3111 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3112 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3126 struct fw_ohci *ohci = fw_ohci(base->card);
3132 index = ctx - ohci->it_context_list;
3133 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3138 index = ctx - ohci->ir_context_list;
3139 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3142 flush_writes(ohci);
3151 struct fw_ohci *ohci = fw_ohci(base->card);
3160 spin_lock_irqsave(&ohci->lock, flags);
3164 index = ctx - ohci->it_context_list;
3165 ohci->it_context_mask |= 1 << index;
3169 index = ctx - ohci->ir_context_list;
3170 ohci->ir_context_mask |= 1 << index;
3171 ohci->ir_context_channels |= 1ULL << base->channel;
3175 index = ctx - ohci->ir_context_list;
3176 ohci->ir_context_mask |= 1 << index;
3177 ohci->ir_context_channels |= ohci->mc_channels;
3178 ohci->mc_channels = 0;
3179 ohci->mc_allocated = false;
3183 spin_unlock_irqrestore(&ohci->lock, flags);
3188 struct fw_ohci *ohci = fw_ohci(base->card);
3195 spin_lock_irqsave(&ohci->lock, flags);
3198 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3199 *channels = ohci->ir_context_channels;
3202 set_multichannel_mask(ohci, *channels);
3206 spin_unlock_irqrestore(&ohci->lock, flags);
3217 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3222 for (i = 0 ; i < ohci->n_ir ; i++) {
3223 ctx = &ohci->ir_context_list[i];
3228 for (i = 0 ; i < ohci->n_it ; i++) {
3229 ctx = &ohci->it_context_list[i];
3317 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3345 struct device *device = ctx->context.ohci->card.device;
3463 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3486 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3498 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3508 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3598 struct fw_ohci *ohci;
3609 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3610 if (ohci == NULL) {
3615 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3627 pci_set_drvdata(dev, ohci);
3629 spin_lock_init(&ohci->lock);
3630 mutex_init(&ohci->phy_reg_mutex);
3632 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3636 ohci_err(ohci, "invalid MMIO resource\n");
3643 ohci_err(ohci, "MMIO resource unavailable\n");
3647 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3648 if (ohci->registers == NULL) {
3649 ohci_err(ohci, "failed to remap registers\n");
3660 ohci->quirks = ohci_quirks[i].flags;
3664 ohci->quirks = param_quirks;
3667 ohci->quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ;
3676 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3678 &ohci->misc_buffer_bus,
3680 if (!ohci->misc_buffer) {
3685 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3690 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3695 err = context_init(&ohci->at_request_ctx, ohci,
3700 err = context_init(&ohci->at_response_ctx, ohci,
3705 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3706 ohci->ir_context_channels = ~0ULL;
3707 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3708 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3709 ohci->ir_context_mask = ohci->ir_context_support;
3710 ohci->n_ir = hweight32(ohci->ir_context_mask);
3711 size = sizeof(struct iso_context) * ohci->n_ir;
3712 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3714 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3715 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3717 if (!ohci->it_context_support) {
3718 ohci_notice(ohci, "overriding IsoXmitIntMask\n");
3719 ohci->it_context_support = 0xf;
3721 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3722 ohci->it_context_mask = ohci->it_context_support;
3723 ohci->n_it = hweight32(ohci->it_context_mask);
3724 size = sizeof(struct iso_context) * ohci->n_it;
3725 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3727 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3732 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2;
3733 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3735 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3738 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3739 reg_read(ohci, OHCI1394_GUIDLo);
3741 if (!(ohci->quirks & QUIRK_NO_MSI))
3745 ohci_driver_name, ohci)) {
3746 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
3751 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3755 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3756 ohci_notice(ohci,
3759 version >> 16, version & 0xff, ohci->card.index,
3760 ohci->n_ir, ohci->n_it, ohci->quirks,
3761 reg_read(ohci, OHCI1394_PhyUpperBound) ?
3767 free_irq(dev->irq, ohci);
3771 kfree(ohci->ir_context_list);
3772 kfree(ohci->it_context_list);
3773 context_release(&ohci->at_response_ctx);
3775 context_release(&ohci->at_request_ctx);
3777 ar_context_release(&ohci->ar_response_ctx);
3779 ar_context_release(&ohci->ar_request_ctx);
3781 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3782 ohci->misc_buffer, ohci->misc_buffer_bus);
3784 pci_iounmap(dev, ohci->registers);
3790 kfree(ohci);
3798 struct fw_ohci *ohci = pci_get_drvdata(dev);
3804 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3805 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3806 flush_writes(ohci);
3808 cancel_work_sync(&ohci->bus_reset_work);
3809 fw_core_remove_card(&ohci->card);
3816 software_reset(ohci);
3817 free_irq(dev->irq, ohci);
3819 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3820 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3821 ohci->next_config_rom, ohci->next_config_rom_bus);
3822 if (ohci->config_rom)
3823 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3824 ohci->config_rom, ohci->config_rom_bus);
3825 ar_context_release(&ohci->ar_request_ctx);
3826 ar_context_release(&ohci->ar_response_ctx);
3827 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3828 ohci->misc_buffer, ohci->misc_buffer_bus);
3829 context_release(&ohci->at_request_ctx);
3830 context_release(&ohci->at_response_ctx);
3831 kfree(ohci->it_context_list);
3832 kfree(ohci->ir_context_list);
3834 pci_iounmap(dev, ohci->registers);
3837 kfree(ohci);
3840 dev_notice(&dev->dev, "removed fw-ohci device\n");
3846 struct fw_ohci *ohci = pci_get_drvdata(dev);
3849 software_reset(ohci);
3852 ohci_err(ohci, "pci_save_state failed\n");
3857 ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
3865 struct fw_ohci *ohci = pci_get_drvdata(dev);
3873 ohci_err(ohci, "pci_enable_device failed\n");
3878 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3879 !reg_read(ohci, OHCI1394_GUIDHi)) {
3880 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3881 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3884 err = ohci_enable(&ohci->card, NULL, 0);
3888 ohci_resume_iso_dma(ohci);