Lines Matching refs:dev_csr
1023 void __iomem *dev_csr;
1061 l3cesr = readl(ctx->dev_csr + L3C_ESR);
1070 l3celr = readl(ctx->dev_csr + L3C_ELR);
1071 l3caelr = readl(ctx->dev_csr + L3C_AELR);
1072 l3cbelr = readl(ctx->dev_csr + L3C_BELR);
1100 writel(0, ctx->dev_csr + L3C_ESR);
1119 val = readl(ctx->dev_csr + L3C_ECR);
1128 writel(val, ctx->dev_csr + L3C_ECR);
1154 writel(0xFFFFFFFF, ctx->dev_csr + L3C_ESR);
1189 void __iomem *dev_csr;
1201 dev_csr = devm_ioremap_resource(edac->dev, &res);
1202 if (IS_ERR(dev_csr)) {
1205 rc = PTR_ERR(dev_csr);
1219 ctx->dev_csr = dev_csr;
1397 reg = readl(ctx->dev_csr + XGICTRANSERRINTSTS);
1409 info = readl(ctx->dev_csr + XGICTRANSERRREQINFO);
1413 writel(reg, ctx->dev_csr + XGICTRANSERRINTSTS);
1417 reg = readl(ctx->dev_csr + GLBL_ERR_STS);
1421 err_addr_lo = readl(ctx->dev_csr + GLBL_SEC_ERRL);
1422 err_addr_hi = readl(ctx->dev_csr + GLBL_SEC_ERRH);
1426 writel(err_addr_lo, ctx->dev_csr + GLBL_SEC_ERRL);
1427 writel(err_addr_hi, ctx->dev_csr + GLBL_SEC_ERRH);
1430 err_addr_lo = readl(ctx->dev_csr + GLBL_MSEC_ERRL);
1431 err_addr_hi = readl(ctx->dev_csr + GLBL_MSEC_ERRH);
1435 writel(err_addr_lo, ctx->dev_csr + GLBL_MSEC_ERRL);
1436 writel(err_addr_hi, ctx->dev_csr + GLBL_MSEC_ERRH);
1442 err_addr_lo = readl(ctx->dev_csr + GLBL_DED_ERRL);
1443 err_addr_hi = readl(ctx->dev_csr + GLBL_DED_ERRH);
1447 writel(err_addr_lo, ctx->dev_csr + GLBL_DED_ERRL);
1448 writel(err_addr_hi, ctx->dev_csr + GLBL_DED_ERRH);
1451 err_addr_lo = readl(ctx->dev_csr + GLBL_MDED_ERRL);
1452 err_addr_hi = readl(ctx->dev_csr + GLBL_MDED_ERRH);
1456 writel(err_addr_lo, ctx->dev_csr + GLBL_MDED_ERRL);
1457 writel(err_addr_hi, ctx->dev_csr + GLBL_MDED_ERRH);
1514 reg = readl(ctx->dev_csr + IOBBATRANSERRINTSTS);
1561 err_addr_lo = readl(ctx->dev_csr + IOBBATRANSERRREQINFOL);
1562 err_addr_hi = readl(ctx->dev_csr + IOBBATRANSERRREQINFOH);
1568 readl(ctx->dev_csr + IOBBATRANSERRCSWREQID));
1569 writel(reg, ctx->dev_csr + IOBBATRANSERRINTSTS);
1580 reg = readl(ctx->dev_csr + IOBPATRANSERRINTSTS);
1603 writel(reg, ctx->dev_csr + IOBPATRANSERRINTSTS);
1607 reg = readl(ctx->dev_csr + IOBAXIS0TRANSERRINTSTS);
1610 err_addr_lo = readl(ctx->dev_csr + IOBAXIS0TRANSERRREQINFOL);
1611 err_addr_hi = readl(ctx->dev_csr + IOBAXIS0TRANSERRREQINFOH);
1617 writel(reg, ctx->dev_csr + IOBAXIS0TRANSERRINTSTS);
1621 reg = readl(ctx->dev_csr + IOBAXIS1TRANSERRINTSTS);
1624 err_addr_lo = readl(ctx->dev_csr + IOBAXIS1TRANSERRREQINFOL);
1625 err_addr_hi = readl(ctx->dev_csr + IOBAXIS1TRANSERRREQINFOH);
1631 writel(reg, ctx->dev_csr + IOBAXIS1TRANSERRINTSTS);
1712 ctx->dev_csr + IOBAXIS0TRANSERRINTMSK);
1714 ctx->dev_csr + IOBAXIS1TRANSERRINTMSK);
1716 ctx->dev_csr + XGICTRANSERRINTMSK);
1728 void __iomem *dev_csr;
1741 dev_csr = devm_ioremap_resource(edac->dev, &res);
1742 if (IS_ERR(dev_csr)) {
1745 rc = PTR_ERR(dev_csr);
1759 ctx->dev_csr = dev_csr;