Lines Matching refs:ctx
145 struct xgene_edac_mc_ctx *ctx = mci->pvt_info;
151 ctx->mcu_csr + MCUESRRA0 + i * MCU_RANK_STRIDE);
176 struct xgene_edac_mc_ctx *ctx = mci->pvt_info;
185 xgene_edac_pcp_rd(ctx->edac, PCPHPERRINTSTS, &pcp_hp_stat);
186 xgene_edac_pcp_rd(ctx->edac, PCPLPERRINTSTS, &pcp_lp_stat);
193 reg = readl(ctx->mcu_csr + MCUESRR0 + rank * MCU_RANK_STRIDE);
208 bank = readl(ctx->mcu_csr + MCUEBLRR0 +
210 col_row = readl(ctx->mcu_csr + MCUERCRR0 +
212 count = readl(ctx->mcu_csr + MCUSBECNT0 +
226 writel(0x0, ctx->mcu_csr + MCUEBLRR0 + rank * MCU_RANK_STRIDE);
227 writel(0x0, ctx->mcu_csr + MCUERCRR0 + rank * MCU_RANK_STRIDE);
228 writel(0x0, ctx->mcu_csr + MCUSBECNT0 +
230 writel(reg, ctx->mcu_csr + MCUESRR0 + rank * MCU_RANK_STRIDE);
234 reg = readl(ctx->mcu_csr + MCUGESR);
243 writel(reg, ctx->mcu_csr + MCUGESR);
249 struct xgene_edac_mc_ctx *ctx = mci->pvt_info;
255 mutex_lock(&ctx->edac->mc_lock);
267 ctx->edac->mc_registered_mask |= 1 << ctx->mcu_id;
270 if (ctx->edac->mc_registered_mask ==
271 ctx->edac->mc_active_mask) {
273 xgene_edac_pcp_clrbits(ctx->edac, PCPHPERRINTMSK,
276 xgene_edac_pcp_clrbits(ctx->edac, PCPLPERRINTMSK,
281 val = readl(ctx->mcu_csr + MCUGECR);
286 writel(val, ctx->mcu_csr + MCUGECR);
289 val = readl(ctx->mcu_csr + MCUGECR);
294 writel(val, ctx->mcu_csr + MCUGECR);
297 xgene_edac_pcp_setbits(ctx->edac, PCPHPERRINTMSK,
299 xgene_edac_pcp_setbits(ctx->edac, PCPLPERRINTMSK,
303 ctx->edac->mc_registered_mask &= ~(1 << ctx->mcu_id);
306 mutex_unlock(&ctx->edac->mc_lock);
309 static int xgene_edac_mc_is_active(struct xgene_edac_mc_ctx *ctx, int mc_idx)
314 if (regmap_read(ctx->edac->csw_map, CSW_CSWCR, ®))
322 if (regmap_read(ctx->edac->mcbb_map, MCBADDRMR, ®))
330 if (regmap_read(ctx->edac->mcba_map, MCBADDRMR, ®))
336 if (!ctx->edac->mc_active_mask)
337 ctx->edac->mc_active_mask = mcu_mask;
347 struct xgene_edac_mc_ctx *ctx;
387 sizeof(*ctx));
393 ctx = mci->pvt_info;
394 *ctx = tmp_ctx; /* Copy over resource value */
395 ctx->name = "xgene_edac_mc_err";
396 ctx->mci = mci;
398 mci->ctl_name = ctx->name;
399 mci->dev_name = ctx->name;
421 list_add(&ctx->next, &edac->mcus);
522 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info;
526 pg_f = ctx->pmd_csr + cpu_idx * CPU_CSR_STRIDE + CPU_MEMERR_CPU_PAGE;
533 ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val,
573 ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val,
617 ctx->pmd * MAX_CPU_PER_PMD + cpu_idx, val,
661 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info;
669 pg_e = ctx->pmd_csr + CPU_MEMERR_L2C_PAGE;
677 ctx->pmd, val, val_hi, val_lo);
722 pg_d = ctx->pmd_csr + CPU_L2C_PAGE;
729 ctx->pmd, val, val_hi, val_lo);
736 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info;
740 xgene_edac_pcp_rd(ctx->edac, PCPHPERRINTSTS, &pcp_hp_stat);
741 if (!((PMD0_MERR_MASK << ctx->pmd) & pcp_hp_stat))
755 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info;
756 void __iomem *pg_f = ctx->pmd_csr + cpu * CPU_CSR_STRIDE +
770 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info;
771 void __iomem *pg_d = ctx->pmd_csr + CPU_L2C_PAGE;
772 void __iomem *pg_e = ctx->pmd_csr + CPU_MEMERR_L2C_PAGE;
777 if (ctx->version > 1)
784 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info;
790 xgene_edac_pcp_clrbits(ctx->edac, PCPHPERRINTMSK,
791 PMD0_MERR_MASK << ctx->pmd);
793 xgene_edac_pcp_setbits(ctx->edac, PCPHPERRINTMSK,
794 PMD0_MERR_MASK << ctx->pmd);
811 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info;
816 cpux_pg_f = ctx->pmd_csr + i * CPU_CSR_STRIDE +
837 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info;
838 void __iomem *pg_e = ctx->pmd_csr + CPU_MEMERR_L2C_PAGE;
863 struct xgene_edac_pmd_ctx *ctx = edac_dev->pvt_info;
867 if (!IS_ENABLED(CONFIG_EDAC_DEBUG) || !ctx->edac->dfs)
870 snprintf(name, sizeof(name), "PMD%d", ctx->pmd);
871 dbgfs_dir = edac_debugfs_create_dir_at(name, ctx->edac->dfs);
890 struct xgene_edac_pmd_ctx *ctx;
915 edac_dev = edac_device_alloc_ctl_info(sizeof(*ctx),
923 ctx = edac_dev->pvt_info;
924 ctx->name = "xgene_pmd_err";
925 ctx->pmd = pmd;
926 ctx->edac = edac;
927 ctx->edac_dev = edac_dev;
928 ctx->ddev = *edac->dev;
929 ctx->version = version;
930 edac_dev->dev = &ctx->ddev;
931 edac_dev->ctl_name = ctx->name;
932 edac_dev->dev_name = ctx->name;
940 ctx->pmd_csr = devm_ioremap_resource(edac->dev, &res);
941 if (IS_ERR(ctx->pmd_csr)) {
944 rc = PTR_ERR(ctx->pmd_csr);
963 list_add(&ctx->next, &edac->pmds);
969 dev_info(edac->dev, "X-Gene EDAC PMD%d registered\n", ctx->pmd);
1055 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
1061 l3cesr = readl(ctx->dev_csr + L3C_ESR);
1070 l3celr = readl(ctx->dev_csr + L3C_ELR);
1071 l3caelr = readl(ctx->dev_csr + L3C_AELR);
1072 l3cbelr = readl(ctx->dev_csr + L3C_BELR);
1100 writel(0, ctx->dev_csr + L3C_ESR);
1102 if (ctx->version <= 1 &&
1116 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
1119 val = readl(ctx->dev_csr + L3C_ECR);
1128 writel(val, ctx->dev_csr + L3C_ECR);
1133 xgene_edac_pcp_clrbits(ctx->edac, PCPHPERRINTMSK,
1135 xgene_edac_pcp_clrbits(ctx->edac, PCPLPERRINTMSK,
1138 xgene_edac_pcp_setbits(ctx->edac, PCPHPERRINTMSK,
1140 xgene_edac_pcp_setbits(ctx->edac, PCPLPERRINTMSK,
1151 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
1154 writel(0xFFFFFFFF, ctx->dev_csr + L3C_ESR);
1167 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
1171 if (!IS_ENABLED(CONFIG_EDAC_DEBUG) || !ctx->edac->dfs)
1174 snprintf(name, sizeof(name), "l3c%d", ctx->edac_idx);
1175 dbgfs_dir = edac_debugfs_create_dir_at(name, ctx->edac->dfs);
1187 struct xgene_edac_dev_ctx *ctx;
1210 edac_dev = edac_device_alloc_ctl_info(sizeof(*ctx),
1218 ctx = edac_dev->pvt_info;
1219 ctx->dev_csr = dev_csr;
1220 ctx->name = "xgene_l3_err";
1221 ctx->edac_idx = edac_idx;
1222 ctx->edac = edac;
1223 ctx->edac_dev = edac_dev;
1224 ctx->ddev = *edac->dev;
1225 ctx->version = version;
1226 edac_dev->dev = &ctx->ddev;
1227 edac_dev->ctl_name = ctx->name;
1228 edac_dev->dev_name = ctx->name;
1246 list_add(&ctx->next, &edac->l3s);
1390 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
1397 reg = readl(ctx->dev_csr + XGICTRANSERRINTSTS);
1409 info = readl(ctx->dev_csr + XGICTRANSERRREQINFO);
1413 writel(reg, ctx->dev_csr + XGICTRANSERRINTSTS);
1417 reg = readl(ctx->dev_csr + GLBL_ERR_STS);
1421 err_addr_lo = readl(ctx->dev_csr + GLBL_SEC_ERRL);
1422 err_addr_hi = readl(ctx->dev_csr + GLBL_SEC_ERRH);
1426 writel(err_addr_lo, ctx->dev_csr + GLBL_SEC_ERRL);
1427 writel(err_addr_hi, ctx->dev_csr + GLBL_SEC_ERRH);
1430 err_addr_lo = readl(ctx->dev_csr + GLBL_MSEC_ERRL);
1431 err_addr_hi = readl(ctx->dev_csr + GLBL_MSEC_ERRH);
1435 writel(err_addr_lo, ctx->dev_csr + GLBL_MSEC_ERRL);
1436 writel(err_addr_hi, ctx->dev_csr + GLBL_MSEC_ERRH);
1442 err_addr_lo = readl(ctx->dev_csr + GLBL_DED_ERRL);
1443 err_addr_hi = readl(ctx->dev_csr + GLBL_DED_ERRH);
1447 writel(err_addr_lo, ctx->dev_csr + GLBL_DED_ERRL);
1448 writel(err_addr_hi, ctx->dev_csr + GLBL_DED_ERRH);
1451 err_addr_lo = readl(ctx->dev_csr + GLBL_MDED_ERRL);
1452 err_addr_hi = readl(ctx->dev_csr + GLBL_MDED_ERRH);
1456 writel(err_addr_lo, ctx->dev_csr + GLBL_MDED_ERRL);
1457 writel(err_addr_hi, ctx->dev_csr + GLBL_MDED_ERRH);
1465 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
1471 if (!ctx->edac->rb_map)
1481 if (regmap_read(ctx->edac->rb_map, RBCSR, ®))
1487 if (regmap_read(ctx->edac->rb_map, RBEIR, ®))
1506 if (regmap_write(ctx->edac->rb_map, RBEIR, 0))
1508 if (regmap_write(ctx->edac->rb_map, RBCSR, 0))
1514 reg = readl(ctx->dev_csr + IOBBATRANSERRINTSTS);
1561 err_addr_lo = readl(ctx->dev_csr + IOBBATRANSERRREQINFOL);
1562 err_addr_hi = readl(ctx->dev_csr + IOBBATRANSERRREQINFOH);
1568 readl(ctx->dev_csr + IOBBATRANSERRCSWREQID));
1569 writel(reg, ctx->dev_csr + IOBBATRANSERRINTSTS);
1574 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
1580 reg = readl(ctx->dev_csr + IOBPATRANSERRINTSTS);
1603 writel(reg, ctx->dev_csr + IOBPATRANSERRINTSTS);
1607 reg = readl(ctx->dev_csr + IOBAXIS0TRANSERRINTSTS);
1610 err_addr_lo = readl(ctx->dev_csr + IOBAXIS0TRANSERRREQINFOL);
1611 err_addr_hi = readl(ctx->dev_csr + IOBAXIS0TRANSERRREQINFOH);
1617 writel(reg, ctx->dev_csr + IOBAXIS0TRANSERRINTSTS);
1621 reg = readl(ctx->dev_csr + IOBAXIS1TRANSERRINTSTS);
1624 err_addr_lo = readl(ctx->dev_csr + IOBAXIS1TRANSERRREQINFOL);
1625 err_addr_hi = readl(ctx->dev_csr + IOBAXIS1TRANSERRREQINFOH);
1631 writel(reg, ctx->dev_csr + IOBAXIS1TRANSERRINTSTS);
1636 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
1643 xgene_edac_pcp_rd(ctx->edac, PCPHPERRINTSTS, &pcp_hp_stat);
1644 xgene_edac_pcp_rd(ctx->edac, PCPLPERRINTSTS, &pcp_lp_stat);
1645 xgene_edac_pcp_rd(ctx->edac, MEMERRINTSTS, ®);
1668 if (ctx->version == 1)
1689 struct xgene_edac_dev_ctx *ctx = edac_dev->pvt_info;
1694 xgene_edac_pcp_clrbits(ctx->edac, PCPHPERRINTMSK,
1699 xgene_edac_pcp_clrbits(ctx->edac, PCPLPERRINTMSK,
1702 xgene_edac_pcp_setbits(ctx->edac, PCPHPERRINTMSK,
1707 xgene_edac_pcp_setbits(ctx->edac, PCPLPERRINTMSK,
1712 ctx->dev_csr + IOBAXIS0TRANSERRINTMSK);
1714 ctx->dev_csr + IOBAXIS1TRANSERRINTMSK);
1716 ctx->dev_csr + XGICTRANSERRINTMSK);
1718 xgene_edac_pcp_setbits(ctx->edac, MEMERRINTMSK,
1727 struct xgene_edac_dev_ctx *ctx;
1750 edac_dev = edac_device_alloc_ctl_info(sizeof(*ctx),
1758 ctx = edac_dev->pvt_info;
1759 ctx->dev_csr = dev_csr;
1760 ctx->name = "xgene_soc_err";
1761 ctx->edac_idx = edac_idx;
1762 ctx->edac = edac;
1763 ctx->edac_dev = edac_dev;
1764 ctx->ddev = *edac->dev;
1765 ctx->version = version;
1766 edac_dev->dev = &ctx->ddev;
1767 edac_dev->ctl_name = ctx->name;
1768 edac_dev->dev_name = ctx->name;
1784 list_add(&ctx->next, &edac->socs);
1813 struct xgene_edac *ctx = dev_id;
1819 xgene_edac_pcp_rd(ctx, PCPHPERRINTSTS, &pcp_hp_stat);
1820 xgene_edac_pcp_rd(ctx, PCPLPERRINTSTS, &pcp_lp_stat);
1826 list_for_each_entry(mcu, &ctx->mcus, next)
1830 list_for_each_entry(pmd, &ctx->pmds, next) {
1835 list_for_each_entry(node, &ctx->l3s, next)
1838 list_for_each_entry(node, &ctx->socs, next)